AK4558EN Datasheet, PDF (67/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ DAC Output (LOUT, ROUT pin)
1. When the PS pin = “L”( “H”), settings by registers(pins) shown below are valid.
LOUT and ROUT pins output VCOM voltage. The load impedance is 5k (min.). When PMDAL/R bits =
LOPS bit = “0”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by
100k (typ). When the LOPS bit is “1”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMDAL/R bits when LOPS bit = “0”. In this case, output
signal line should be pulled-down by 20k after AC coupled as Figure 49. Rise/Fall time is 300ms (max.)
when C=1F and R_L=10k. When PMDAL/R bits = “1” and LOPS bit = “0”, the DAC output is in normal
operation.
LOPS bit
0
1
PMDAL
Mode
LOUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 33. Lch DAC Output Mode Setting
(default)
LOPS bit
0
1
PMDAR
Mode
ROUT pin
0
Power-down
Pull-down to VSS1
1
Normal Operation Normal Operation
0
Power-save
Fall down to VSS1
1
Power-save
Rise up to VCOM
Table 34. Rch DAC Output Mode Setting
(default)
LOUT 1F
ROUT
220
20k
Figure 49. External Circuit of DAC Output (in case of using a Pop Noise Reduction Circuit)
015004500-E-02
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2015/09