AK4558EN Datasheet, PDF (69/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
[DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)]
PMDAL/R pins
LOPS pin
(2)
(1)
(3)
300 ms
LOUT, ROUT pins
Normal Output
(5)
(4)
(6)
300 ms
99%VCOM
1%VCOM
300 ms
300 ms
Figure 52. DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOPS pin = “H”. DAC output enters power-save mode.
(2) Set PMDAL/R pin = “H”. DAC output exits power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) when
C=1F.
(3) Set LOPS pin = “L” after LOUT and ROUT pins rise up. Stereo line output exits power-save mode.
Stereo line output is enabled.
(4) Set LOPS pin = “H”. Stereo line output enters power-save mode.
(5) Set PMDAL/R pin = “L”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max
300ms) at C=1F.
(6) Set LOPS pin = “L” after LOUT and ROUT pins fall down. Stereo line output exits power-save
mode.
015004500-E-02
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2015/09