AK4558EN Datasheet, PDF (46/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ PLL Unlock State
PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins = “HH”)
In this mode, LRCK and BICK pins output “L” until the PLL goes to lock state after PMPLL bit = “0” → “1”.
(Table 20).
After PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to
normal state after a period of 1/fs.
To avoid invalid outputs of BICK and LRCK pins, set PMPLL bit = “0” once when changing sampling
frequency. It enables to output “L” signal without invalid clocks.
PLL State
BICK pin
LRCK pin
After PMPLL bit “0” → “1”
“L” Output
“L” Output
PLL Unlock (except the case above)
Invalid
Invalid
PLL Lock
Table 21
1fs Output
Table 20. Clock Operation at PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins =”HH”)
■ PLL Master Mode (PMPLL bit = “1”, CKS3-2 pins = “HH”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 19MHz, 24MHz, 26MHz or
27MHz) is input to the MCKI pin, the internal PLL circuit generates BICK and LRCK clocks. The BICK
output frequency is selected from 32fs, 64fs, 128fs and 256fs by BCKO1-0 bits (Table 21).
AK4558
11.2896MHz, 12MHz, 12.288MHz, 13MHz
13.5MHz, 19.2MHz, 24MHz, 26MHz, 27MHz
DSP or P
MCKI
BICK
LRCK
32fs, 64fs or
128fs(TDM128),
256fs(TDM256)
1fs
BCLK
LRCK
SDTO
SDTI
SDTI
SDTO
Figure 14. PLL Master Mode
Mode
0
1
2
3
BCKO1 bit
BCKO0 bit
BICK Output Frequency BICK Output Frequency
(Stereo mode)
(TDM mode)
0
0
32fsn,32fsd,32fsq
N/A (Note 39)
0
1
64fsn,64fsd,64fsq
N/A (Note 39)
1
0
128fsn, 128fsd
N/A (Note 39)
1
1
256fsn
256fsn,256fsd,128fsq
Table 21. BICK Output Frequency at Master Mode (N/A: Not Available)
(default)
Note 39. Mode0, Mode1 and Mode2 cannot be used in TDM modes.
015004500-E-02
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2015/09