AK4558EN Datasheet, PDF (41/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ PLL Mode (PMPLL bit = “1”)
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is
selected by the PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4558 is supplied stable clocks or
the sampling frequency is changed after PLL is powered-up (PMPLL bit = “0” → “1”), are shown in Table
16. In Mode 15 (LRCK reference), the VCOC pin must be connected to VSS via a 10nF capacitor. In
other modes, the VCOC pin must be connected to VSS directly.
1) PLL Mode Setting
Mode
PLL3
bit
PLL2
bit
PLL1
bit
PLL0
bit
PLL Reference
Clock Input Pin
Input
Frequency
Connection
of
VCOC pin
C[F]
PLL Lock
Time
(max)
0
0
0
0
0
BICK pin
256fs
VSS
2ms
1
0
0
0
1
BICK pin
128fs
VSS
2ms
2
0
0
1
0
BICK pin
64fs
VSS
2ms
3
0
0
1
1
BICK pin
32fs
VSS
2ms (default)
4
0
1
0
0
MCKI pin
11.2896MHz
VSS
10ms (Note 35)
5
0
1
0
1
MCKI pin
12.288MHz
VSS
10ms (Note 36)
6
0
1
1
0
MCKI pin
12MHz
VSS
10ms
7
0
1
1
1
MCKI pin
24MHz
VSS
10ms
8
1
0
0
0
MCKI pin
19.2MHz
VSS
10ms
10
1
0
1
0
MCKI pin
13MHz
VSS
10ms
11
1
0
1
1
MCKI pin
26MHz
VSS
10ms
12
1
1
0
0
MCKI pin
13.5MHz
VSS
10ms
13
1
1
0
1
MCKI pin
27MHz
VSS
10ms
15
1
1
1
1
LRCK pin
1fs
10n
 50%
40ms
Table 16. Setting of PLL Mode (fs: Sampling Frequency)
Note 35. The AK4558 should be in EXT Master Mode when fs = 22.05kHz or 44.1kHz.
Note 36. The AK4558 should be in EXT Master Mode when fs = 16kHz, 24kHz, 32kHz or 48kHz.
015004500-E-02
- 41 -
2015/09