AK4558EN Datasheet, PDF (76/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

3-2. PS pin = “H”
[AK4558]
CKS3-0 pins
XXXX
LOPS pin
PMDAL/R pins
LOUT pin
ROUT pin
>300 ms
(1) ₍₂₎
(3)
>300 ms
(4)
(6)
(5)
<300 ms
Normal Output
<300 ms
Figure 60. DAC Sequence (PS pin = “H”)
<Sequence>
At first, set operation mode by the CKS3-0 pins according to “Parallel Control Mode”.
In parallel mode, digital filter setting is Short delay Sharp Roll-Off Filter mode. Digital filter does not
correspond to PLL and TDM mode.
(1) Set the DAC output to power-save mode: LOPS pin “L” → “H”
(2) Power up the DAC: PMDAL = PMDAR pins = “L” → “H”
Outputs of the LOUT and ROUT pins start rising. Rise time is 300ms (max.) when C = 1µF.
(3) Release power-save mode of the DAC output (LOPS pin = “H” → “L”) after the LOUT and the ROUT
pins are risen up. Then data output is started from the LOUT and the ROUT pins.
(4) Set the DAC output to power-save mode: LOPS pin “L” → “H”
(5) Power down the DAC: PMDAL = PMDAR pins = “H” → “L”
Outputs of the LOUT and the ROUT pins go to low. The maximum fall time is 300 ms when C = 1 uF.
(6) Release power-save mode of the DAC output: LOPS pin = “H” → “L”
Set LOPS pin to “L” after output of the LOUT and ROUT pins fall to “L”.
015004500-E-02
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2015/09