AK4558EN Datasheet, PDF (28/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
Parameter
Symbol
Min. Typ. Max. Unit
Control Interface Timing (I²C Bus):
SCL Clock Frequency
fSCL
-
Bus Free Time Between Transmissions
tBUF
1.3
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
Clock Low Time
tLOW
1.3
Clock High Time
tHIGH
0.6
Setup Time for Repeated Start Condition
tSU:STA 0.6
SDA Hold Time from SCL Falling (Note 30)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT 0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO 0.6
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
Capacitive load on bus
Cb
-
-
400 ^kHz
-
-
s
-
-
s
-
-
s
-
-
s
-
-
s
-
-
s
-
-
s
-
1.0 ^s
-
0.3 ^s
-
-
s
-
50
ns
-
400 ^pF
Power-down & Reset Timing
PDN Accept Pulse Width
(Note 31)
tAPD
150
-
-
ns
PDN Reject Pulse Width
tRPD
-
-
30 ns
PDN “” to SDTO valid
(Note 32)
tPDV
-
5200
- 1/fs
Note 30. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 31. The AK4558 can be reset by setting the PDN pin to “L” upon power-up.
The PDN pin must held “L” for more than 150ns for a certain reset. The AK4558 is not reset by
the “L” pulse less than 30ns.
Note 32. This cycle is the numbers of LRCK rising from the PDN pin rising. (Internal power-down is
released in 5ms (max.) after the PDN pin = “H”)
015004500-E-02
- 28 -
2015/09