AK4558EN Datasheet, PDF (29/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ Timing Diagram
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
LRCK
BICK
1/fsn, 1/fsd, 1/fsq
tdLRKH
tdLRKL
tBCK
tBCKH
tBCKL
VIH
VIL
Duty
= tdLRKH (or tdLRKL) x fs x 100
VIH
VIL
Figure 2. Clock Timing (TDM1-0 bits = “00” & Slave Mode)
1/fCLK
VIH
MCKI
VIL
tCLKH
tCLKL
1/fs
VIH
LRCK
VIL
tLRH
tLRL
tBCK
VIH
BICK
VIL
tBCKH
tBCKL
Figure 3. Clock Timing (Except TDM1-0 bits = “00” & Slave Mode)
015004500-E-02
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2015/09