AK4558EN Datasheet, PDF (68/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
[DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)]
PMDAL/R bits
LOPS bit
(2)
(1)
(3)
300 ms
LOUT, ROUT pins
Normal Output
(5)
(4)
(6)
300 ms
99%VCOM
1%VCOM
300 ms
300 ms
Figure 50. DAC Output Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOPS bit = “1”. DAC output enters power-save mode.
(2) Set PMDAL/R bits = “1”. DAC output exits power-down mode.
LOUT and ROUT pins rise up to VCOM voltage. Rise time is 200ms (max 300ms) when
C=1F.
(3) Set LOPS bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits power-save mode.
Stereo line output is enabled.
(4) Set LOPS bit = “1”. Stereo line output enters power-save mode.
(5) Set PMDAL/R bits = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max
300ms) at C=1F.
(6) Set LOPS bit = “0” after LOUT and ROUT pins fall down. Stereo line output exits power-save
mode.
2. When the PS pin = “H”, settings shown below are valid.
LOUT and ROUT pins output VCOM voltage. The load impedance is 5k (min.). When PMDAL/R pins =
LOPS pin = “L”, the stereo line output enters power-down mode and the output is pulled-down to VSS1 by
100k (typ). When the LOPS pin is “H”, stereo line output enters power-save mode. Pop noise at
power-up/down can be reduced by changing PMDAL/R pins. In this case, output signal line should be
pulled-down by 20k after AC coupled as Figure 51. Rise/Fall time is 300ms (max.) when C=1F and
R_L=10k. When PMDAL/R pins = “H” and LOPS pin = “L”, the stereo lineout is in normal operation.
LOUT 1F
ROUT
220
20k
Figure 51. External Circuit of DAC Output (in case of using a Pop Noise Reduction Circuit)
015004500-E-02
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2015/09