AK4558EN Datasheet, PDF (70/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ Control Sequence
1. Clock Set Up
When the AK4558 is in operation, the clocks must be supplied.
1-1. PLL Master Mode(PS pin=“L”, CKS3-2 pins = “H H”)
Power Supply
PDN pin
Internal PDN
PMPLL bit
(Addr:01H, D0)
MCKI pin
BICK pin
LRCK pin
(1)
(2)
1ms (min) (LDOE=”L”), 10ms (min) (LDOE=”H”)
(3)
(4)
10ms (max)
(5)
Input
(6)
Output
Example:
Audio I/F Format: 32bit I2S (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
Sampling Frequency: 44.1kHz
(1) Power Supply & PDN pin = “L”  “H”
(3)Addr:01H, Data:08H
Addr:03H, Data:38H
Addr:05H, Data:3AH
(4)Addr:01H, Data:09H
BICK and LRCK output
Figure 53. Clock Set Up Sequence (1)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 150ns or more is needed to reset the AK4558.
(2) Control register settings become available in 10ms (min.) when LDOE pin = “H”, or 1ms (min.)
when LDOE pin = “L”, after the PDN pin “L” → “H”.
(3) DIF2-0, PLL3-0, FS3-0 and BCKO1-0 bits must be set during this period.
(4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external
source. PLL lock time is 10ms (max). In this period, the AK4558 outputs BICK and LRCK as it is
in EXT, Master mode if a clock is supplied to the MCKI pin during the period (3).
(5) The AK4558 starts outputting the LRCK and BICK clocks after the PLL became stable. Then
normal operation starts.
015004500-E-02
- 70 -
2015/09