AK4558EN Datasheet, PDF (47/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ PLL Slave Mode (PMPLL bit = “1”, CKS3-2 pins = “LL” or “LH” or “HL”)
A reference clock of PLL is selected among the input clocks to the BICK pin or the LRCK pin. The
required clock for the AK4558 is generated by an internal PLL circuit. Input frequency is selected by
PLL3-0 bits (Table 16).
a) PLL Reference Clock: BICK pin
The required clock for the AK4558 is generated by an internal PLL circuit with the BICK input clock. PLL
reference clock is selected by PLL3-0 bits. BICK and LRCK inputs must be synchronized. 8kHz ~ 216kHz
sampling frequency is supported and it can be set by FS3-0 bits (Table 17).
AK4558
MCKI
BICK
LRCK
SDTO
SDTI
DSP or P
32fs, 64fs or
128fs(TDM128) or
256fs(TDM256)
1fs
BCLK
LRCK
SDTI
SDTO
Figure 15. PLL Slave Mode 1 (PLL Reference Clock: BICK pin)
b) PLL Reference Clock: LRCK pin
The required clock for the AK4558 is generated by an internal PLL circuit with the LRCK input clock. Set
PLL3-0 bits = “1111”. BICK and LRCK inputs must be synchronized. 8kHz ~ 216kHz sampling frequency
is supported and it can be set by FS3-0 bits (Table 17).
AK4558
MCKI
BICK
LRCK
SDTO
SDTI
DSP or P
32fs, 64fs or
128fs(TDM128) or
256fs(TDM256)
1fs
BCLK
LRCK
SDTI
SDTO
Figure 16. PLL Slave Mode 2 (PLL Reference Clock: LRCK pin)
015004500-E-02
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2015/09