AK4558EN Datasheet, PDF (42/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
2) Sampling Frequency Setting in PLL Mode
When the PLL reference clock input is the MCKI pin, the sampling frequency is selected by FS3-0 bits as
defined in Table 17.
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency (Note 37)
0
0
0
0
0
8kHz mode
1
0
0
0
1
11.025kHz mode
2
0
0
1
0
12kHz mode
3
0
0
1
1
16kHz mode
4
0
1
0
0
22.05kHz mode
5
0
1
0
1
24kHz mode
(default)
6
0
1
1
0
32kHz mode
7
0
1
1
1
44.1kHz mode
8
1
0
0
0
48kHz mode
9
1
0
0
1
64kHz mode
10
1
0
1
0
88.2 kHz mode
11
1
0
1
1
96 kHz mode
12
1
1
0
0
128 kHz mode
13
1
1
0
1
176.4 kHz mode
14
1
1
1
0
192 kHz mode
15
1
1
1
1
192 kHz mode
Table 17. Setting of Sampling Frequency at PMPLL bit = “1”
Note 37. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL
differs from the sampling frequency of mode name in some combinations of MCKI
frequency(PLL3-0 bits) and sampling frequency (FS3-0 bits). Refer to Table 19 for the details of
sampling frequency. In master mode, LRCK and BICK output frequency correspond to sampling
frequencies shown in Table 19.
When the PLL reference clock input is the LRCK pin or the BICK pin, the sampling frequency is selected
by FS3-1 bits as defined in Table 18. When the BICK pin is the PLL reference clock input, the sampling
frequency generated by PLL is the same sampling frequency of mode name.
Mode FS3 bit FS2 bit FS1 bit FS0 bit Sampling Frequency Range
0
0
0
0
x
8kHz  fs  13.5kHz
1
0
0
1
x
12kHz < fs  27kHz
2
0
1
0
x
24kHz < fs  54kHz
(default)
3
0
1
1
x
48kHz < fs  108kHz
4
1
0
0
x
96kHz < fs  216kHz
Others
Others
N/A
Table 18. Setting of Sampling Frequency at PLL3-2 bits = “00” or PLL3-0 bits = “1111”, and PMPLL bit =
“1” in PLL Slave Mode (PLL Mode 0-3: BICK Reference, Mode15: LRCK Reference)
(PLL Reference Clock: LRCK or BICK pin), (x: Do not care, N/A: Not Available)
015004500-E-02
- 42 -
2015/09