AK4558EN Datasheet, PDF (81/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
■ Serial Control Interface
I²C-bus Control Mode (PS pin = “L”)
Functions of the AK4558 are controlled by registers or pins. The register writing is executed via I²C bus.
The chip address is determined by the state of the CAD0 and CAD1 inputs. Setting the PDN pin = “L”
initializes the registers to their default values. Writing “0” to the RSTN bit can initialize the internal timing
circuit, but the register values will not be initialized.
* A control register writing is not available when the PDN pin = “L”.
The AK4558 supports the fast-mode I²C-bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins
must be connected to the voltage that is equal to or less than (TVDD+03)V.
1. WRITE Operations
Figure 68 shows the data transfer sequence for the I²C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 74). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bit). These bits identify
the specific device on the bus. The hard-wired input pins (CAD1 and CAD0) set these device address bits
(Figure 69). If the slave address matches that of the AK4558, the AK4558 generates an acknowledge
and the operation is executed. The master must generate the acknowledge-related clock pulse and
release the SDA line (HIGH) during the acknowledge clock pulse (Figure 75). A R/W bit value of “1”
indicates that the read operation is to be executed, and “0” indicates that the write operation is to be
executed.
The second byte consists of the control register address of the AK4558. The format is MSB first, and
those most significant 1bit is fixed to zero (Figure 70). The data after the second byte contains control
data. The format is MSB first, 8bits (Figure 71). The AK4558 generates an acknowledge after each byte
is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 74).
The AK4558 can perform more than one byte write operation per sequence. After receipt of the third byte
the AK4558 generates an acknowledge and awaits the next data. The master can transmit more than
one byte instead of terminating the write cycle after the first data byte is transferred. After receiving each
data packet the internal address counter is incremented by one, and the next data is automatically taken
into the next address. If the address exceeds “09H” prior to generating a stop condition, the address
counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 76) except for
the START and STOP conditions.
S
T
S
A
R/W="0"
T
R
O
T
P
SDA
S lave
S _Address
S ub
A ddress(n)
Data(n)
Data(n+1)
Data(n+x)
P
A
A
A
A
A
A
C
C
C
C
C
C
K
K
K
K
K
K
Figure 68. Data Transfer Sequence in I²C Bus Mode
0
0
1
0
0 CAD1 CAD0 R/W
Figure 69. The First Byte (CAD1 and CAD0 are set by pin settings)
015004500-E-02
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2015/09