AK4558EN Datasheet, PDF (22/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
PLL Slave Mode (PLL Reference Clock = LRCK pin)
LRCK Input Timing
Frequency
Normal Speed Mode: 256fs, 512fs
fsn
8
-
54
kHz
384fs, 768fs
8
-
48
kHz
Double Speed Mode: 256fs
fsd
54
-
108
kHz
384fs
48
-
96
kHz
Quad Speed Mode: 128fs
fsq
108
-
216
kHz
192fs
96
-
192
kHz
Stereo Mode: Duty Cycle
Duty
45
-
55
%
TDM128Mode:
I²S compatible: Pulse Width Low
tLRCKL 1/(128fsq)
s
-
127/(128fsq)
s
MSB or LSB justified: Pulse Width High tLRCKH 1/(128fsq)
-
127/(128fsq)
s
TDM256 Mode:
I²S compatible: Pulse Width Low
tLRCKL
1/(256fsn)
1/(256fsd)
-
255/(256fsn)
255/(256fsd)
s
MSB or LSB justified: Pulse Width High tLRCKH
1/(256fsn)
1/(256fsd)
-
255/(256fsn)
255/(256fsd)
s
BICK Input Timing
1/(64fs)
Period Stereo Mode
tBCK
1/(128fsd)
-
1/(32fsn)
s
1/(256fsn)
TDM128 Mode (Note 19) tBCK
-
1/(128fsq)
-
s
TDM256 Mode (Note 19) tBCK
-
1/(256fsn)
1/(256fsd)
-
s
Pulse Width Low
tBCKL 0.4 x tBCK
-
-
s
Pulse Width High
tBCKH 0.4 x tBCK
-
-
s
015004500-E-02
- 22 -
2015/09