AK4558EN Datasheet, PDF (77/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
4. Reset Function
When RSTN bit= “0” analog and digital blocks of the ADC are powered-down and digital block of DAC is
powered-down, but the internal register are not initialized. The analog outputs go to VCOM voltage, and
SDTO pin outputs “L”.
RSTN bit
Internal
RSTN bit
ADC Internal
State
DAC Internal
State
ADC In
(Analog)
ADC Out
(Digital)
DAC In
(Digital)
DAC Out
(Analog)
Normal Operation
1/fs (5)
Power-down
1/fs (6)
(1)
Init Cycle
Normal Operation
Normal Operation
Digital Block Power-down
Normal Operation
GD ⁽²⁾
GD
(3)
“0”data
“0”data
(2)
GD
GD
(7)
(4)
(7)
Clock In
MCKI,LRCK,BICK
Don’t care
Figure 61. Reset Sequence
Note:
(1) The analog section of the ADC is initialized after exiting reset state.
The initializing cycle is 5200fs in Normal Speed Mode (DFS1-0 bits = “00”), 10000fs in Double
Speed Mode (DFS1-0 bits = “01”) and 19200fs in Quad Speed Mode (DFS1-0 bits “10”). In this
period, the ADC input voltage should be operating common voltage.
(2) Digital output corresponding to the analog inputs, and analog outputs corresponding to the digital
inputs have group delay (GD).
(3) The ADC output is “0” data at power-down state.
(4) The DAC output is VCOM voltage at power-down state.
(5) There is a delay, 1/fs from writing RSTN bit = “0” to set the internal RSTN bit = “0”.
(6) There is a delay, 1/fs from writing RSTN bit = “1” to start an initialization cycle.
(7) Click noise occurs at the edges (“ ”) of the internal timing of RSTN. This noise is output even if “0”
data is input. Mute the analog output externally if the click noise (7) adversely affect system
performance.
015004500-E-02
- 77 -
2015/09