AK4558EN Datasheet, PDF (24/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
Parameter
Symbol
Min.
Typ.
Max. Unit
External Master Mode
MCKI Input Timing
External Clock
256fsn:
384fsn:
512fsn, 256fsd, 128fsq:
768fsn, 384fsd, 192fsq:
fCLK
fCLK
fCLK
fCLK
2.048
3.072
4.096
6.144
-
13.824 MHz
-
18.432 MHz
-
27.648 MHz
-
36.864 MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
s
Pulse Width High
tCLKH 0.4/fCLK
-
-
s
LRCK Output Timing
Stereo mode
(TDM1-0 bits = “00”)
Normal Speed Mode: 256fs, 512fs fsn
8
54
384fs, 768fs
Double Speed Mode: 256fs
fsd
8
54
-
48
108
kHz
384fs
48
96
Quad Speed Mode: 128fs
fsq
108
216
192fs
96
192
Stereo Mode: Duty Cycle
Duty
-
50
-
%
TDM256 mode
(Note 23)
(TDM1-0 bits = “1X”)
fsn
8
-
48
kHz
LRCK frequency
I²S compatible: Pulse Width Low
tLRCKL
-
1/(8fsn)
-
s
MSB justified: Pulse Width High
tLRCKH
-
1/(8fsn)
-
s
TDM256 mode
(Note 24)
(TDM1-0 bits = “1X”)
fsd
48
-
96
kHz
LRCK frequency
I²S compatible: Pulse Width Low
tLRCKL
-
1/(8fsd)
-
s
MSB justified: Pulse Width High
tLRCKH
-
1/(8fsd)
-
s
TDM128 mode
(Note 25)
(TDM1-0 bits = “01”)
fsq
96
-
192
kHz
LRCK frequency
I²S compatible: Pulse Width Low
tLRCKL
-
1/(4fsq)
-
s
MSB justified: Pulse Width High
tLRCKH
-
1/(4fsq)
-
s
BICK Output Timing (Table 15)
Period
BCKO1-0 bits = “00” tBCK
-
1/(32fs)
-
s
BCKO1-0 bits = “01” tBCK
-
1/(64fs)
-
s
BCKO1-0 bits = “10” tBCK
-
1/(128fs)
-
s
BCKO1-0 bits = “11” tBCK
-
1/(256fsn)
-
s
1/(256fsn)
TDM Mode
tBCK
-
1/(256fsd)
-
s
1/(128fsq)
Duty Cycle (Note 26)
dBCK
-
50
-
%
Note 23. The AK4558 should be in Normal Speed mode.
Note 24. The AK4558 should be in Double Speed mode.
Note 25. The AK4558 should be in Quad Speed mode.
Note 26. When MCKI = 256fsn or 256fsd and BICK output frequency is 256fs, or when MCKI =
128fsq and BICK output frequency is 128fs, the Duty of BICK is MCKI pulse width.
015004500-E-02
- 24 -
2015/09