AK4558EN Datasheet, PDF (82/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
0
0
0
A4
A3
A2
A1
A0
Figure 70. The Second Byte
D7
D6
D5
D4
D3
D2
D1
D0
Figure 71. Byte Structure after The Second Byte
1. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4558. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds 09H prior to generating stop condition, the address counter will “roll over” to 00H and the data of
00H will be read out.
The AK4558 supports two basic read operations: Current Address Read and Random Address Read.
2-1. Current Address Read
The AK4558 has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
Current Read operation would access data from the address “n+1”. After receipt of the slave address with
R/W bit “1”, the AK4558 generates an acknowledge, transmits 1-byte of data to the address set by the
internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4558 ceases the transmission.
S
T
A
R/W="1"
R
T
SDA
Slave
S _Address
Data(n)
Data(n+1)
Data(n+2)
A
MA
MA
MA
C
AC
AC
AC
K
S
T
K
S
T
K
S
T
K
E
E
E
R
R
R
Figure 72. Current Address Read
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
S
T
K
E
S
T
E
C
K
R
R
2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4558 then generates an acknowledge, 1 byte of data and increments
the internal address counter by 1. If the master does not generate an acknowledge but generates a stop
condition instead, the AK4558 ceases the transmission.
015004500-E-02
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2015/09