AK4558EN Datasheet, PDF (21/94 Pages) Asahi Kasei Microsystems – 108dB 216kHz 32Bit CODEC with PLL

[AK4558]
Parameter
Symbol
PLL Slave Mode (PLL Reference Clock = BICK pin)
LRCK Input Timing
Frequency
Normal Speed Mode: 256fs, 512fs
fsn
384fs, 768fs
Double Speed Mode: 256fs
fsd
384fs
Quad Speed Mode: 128fs
fsq
192fs
Stereo mode duty cycle
Duty
TDM128Mode: (Note 19)
I²S compatible: Pulse Width Low
tLRCKL
MSB or LSB justified: Pulse Width High tLRCKH
TDM256 Mode: (Note 19)
I²S compatible: Pulse Width Low
tLRCKL
MSB or LSB justified: Pulse Width High tLRCKH
BICK Input Timing
Period Stereo Mode
PLL3-0 bits = “0011”
PLL3-0 bits = “0010”
tBCK
tBCK
PLL3-0 bits = “0001”
tBCK
PLL3-0 bits = “0000”
TDM128 Mode
PLL3-0 bits = “0001”
TDM256 Mode
PLL3-0 bits = “0000”
Pulse Width Low
Pulse Width High
tBCK
tBCK
tBCK
tBCKL
tBCKH
Min.
Typ.
Max.
Unit
8
8
54
48
108
96
45
1/(128fsq)
1/(128fsq)
1/(256fsn)
1/(256fsd)
1/(256fsn)
1/(256fsd)
-
54
kHz
-
48
kHz
-
108
kHz
-
96
kHz
-
216
kHz
-
192
kHz
55
%
s
-
127/(128fsq) s
-
127/(128fsq) s
-
255/(256fsn)
255/(256fsd)
s
-
255/(256fsn)
255/(256fsd)
s
-
1/(32fs)
-
s
-
1/(64fs)
-
s
1/(128fsn)
1/(128fsd)
s
-
1/(256fsn)
-
s
-
1/(128fsq)
-
s
1/(256fsn)
-
1/(256fsd)
-
s
0.4 x tBCK
-
-
s
0.4 x tBCK
-
-
s
015004500-E-02
- 21 -
2015/09