XC5VLX110T-2FFG1738I Datasheet, PDF (91/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Date
12/02/08
12/19/08
01/14/09
02/06/09
04/01/09
06/25/09
05/05/10
Version
4.8
4.9
4.10
5.0
5.1
5.2
5.3
Revision
• Added I_IN row to Absolute Maximum Ratings in Table 1, page 1.
• In Table 32, page 16, changed duty cycle values for T_DCREF and added note 2.
• Changed Conditions for T_PHASE in Table 32, page 16 and Table 44, page 22.
• In Table 35, page 18, updated R_XPPMTOL values, updated note 1, and added note 2.
• In Table 45, page 23, updated parameters with separate FXT and TXT values.
• In Table 46, page 23, corrected units of T_LLSKEW.
• In Table 54, page 30, updated SX240T, FXT, and TXT speed grade designations.
• In Table 55, page 31, updated SX240T and FXT rows.
• In Table 58, page 37, added LVCMOS, 1.2V row.
• In Table 59, page 38, corrected V_MEAS value for LVCMOS, 1.2V row.
• In Table 80, page 60, updated note 3 with sentence about global clock tree.
• Updated Table 5, page 6 with power-on current values for XC5VSX240T, XC5VTX150T, XC5VTX240T,
XC5VFX100T, and XC5VFX200T devices.
• In Table 1, page 1, changed note 2 to refer to UG112 for soldering guidelines.
• In Table 54, page 30, moved speed grades for the XC5VTX150T and XC5VTX240T devices to
Production.
• In Table 55, page 31, added the ISE software version for the XC5VTX150T and XC5VTX240T devices.
• In Table 80, page 60, moved the reference to the duty cycle distortion note to apply to both
T_{DUTY_CYC_DLL} and T_{DUTY_CYC_FX}.
• Changed document classification from Advance Product Specification to Product Specification.
• In Table 1, page 1, changed V_IN and added note 5.
• In Table 5, page 6, removed the Max columns and added note 2 about calculating the maximum startup
current.
• In Table 74, page 55, removed LX20T from second row of F_OUTMAX.
• In Table 65, page 44, changed “A – D input” to “AX – DX input” for the T_DICK/T_CKDI parameter.
• In Table 74, page 55, prepended “±” to all speed grade values for the T_OUTDUTY parameter.
• In Table 2, page 2, added note 6.
• In Table 11, page 9, changed V_CCAUX to V_CCO in note 1.
Removed DV_PPIN from the examples in Figure 2 and Figure 7.
In Table 31, changed “GTPDRPCLK” to “GTP DCLK (DRP clock)” in the Description column. In Table 35,
added table note 2 about R_XPPMTOL.
In Table 41, changed the maximum value of V_ISE to 1000 mV.
In Table 42, changed the minimum PLL frequency (F_GPLLMIN) to 1.48 GHz for all three speed grades. In
Table 43, changed “GTXDRPCLK” to “GTX DCLK (DRP clock)” in the Description column. In Table 45,
removed “2 byte or 4 byte interface” from the Conditions column for T_RX and T_TX. In Table 47, added table
note 2 about R_XPPMTOL.
In Table 51, changed the maximum value of AI_DD to 13 mA.
In Table 74, updated description of T_FBDELAY.
Notice of Disclaimer
THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN ("PRODUCTS") ARE SUBJECT TO THE TERMS AND
CONDITIONS OF THE XILINX LIMITED WARRANTY WHICH CAN BE VIEWED AT http://www.xilinx.com/warranty.htm. THIS LIMITED
WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT THAT IS NOT WITHIN THE
SPECIFICATIONS STATED IN THE XILINX DATA SHEET. ALL SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE.
PRODUCTS ARE NOT DESIGNED OR INTENDED TO BE FAIL-SAFE OR FOR USE IN ANY APPLICATION REQUIRING FAIL-SAFE
PERFORMANCE, SUCH AS LIFE-SUPPORT OR SAFETY DEVICES OR SYSTEMS, OR ANY OTHER APPLICATION THAT INVOKES
THE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL
APPLICATIONS"). USE OF PRODUCTS IN CRITICAL APPLICATIONS IS AT THE SOLE RISK OF CUSTOMER, SUBJECT TO
APPLICABLE LAWS AND REGULATIONS.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
91