XC5VLX110T-2FFG1738I Datasheet, PDF (16/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
GTP_DUAL Tile Switching Characteristics
Consult UG196:Virtex-5 FPGA RocketIO GTP Transceiver User Guide for further information.
Table 30: GTP_DUAL Tile Performance
Symbol
Description
F_GTPMAX
F_GPLLMAX
F_GPLLMIN
Maximum GTP transceiver data rate
Maximum PLL frequency
Minimum PLL frequency
Speed Grade
-3
-2
-1
3.75
3.75
3.2
2.0
2.0
2.0
1.0
1.0
1.0
Units
Gb/s
GHz
GHz
Table 31: Dynamic Reconfiguration Port (DRP) in the GTP_DUAL Tile Switching Characteristics
Symbol
Description
Speed Grade
-3
-2
-1
F_GTPDRPCLK GTP DCLK (DRP clock) maximum frequency
200
175
150
Units
MHz
Table 32: GTP_DUAL Tile Reference Clock Switching Characteristics
Symbol
Description
Conditions
F_GCLK
T_RCLK
T_FCLK
T_DCREF
T_GJTT
T_LOCK
T_PHASE
Reference clock frequency range⁽¹⁾
CLK
Reference clock rise time
20% – 80%
Reference clock fall time
80% – 20%
Reference clock duty cycle⁽²⁾
CLK
Reference clock total jitter, peak-peak⁽³⁾ CLK
Clock recovery frequency acquisition
time
Initial PLL lock
Clock recovery phase acquisition time
Lock to data after PLL has
locked to the reference clock
All Speed Grades
Min
Typ
Max
60
350
200
400
200
400
40
50
60
40
1
200
Units
MHz
ps
ps
%
ps
ms
µs
Notes:
1. The clock from the GTP_DUAL differential clock pin pair can be used for all serial bit rates. GREFCLK can be used for serial bit rates up to
1 Gb/s.
2. For reference clock rates above 325 MHz, a duty cycle of 45% to 55% must be maintained.
3. Measured at the package pin. GTP_DUAL jitter characteristics measured using a clock with specification T_GJTT.
X-Ref Target - Figure 5
80%
T_RCLK
20%
T_FCLK
ds202_05_100506
Figure 5: Reference Clock Timing Parameters
DS202 (v5.3) May 5, 2010
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Product Specification
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