XC5VLX110T-2FFG1738I Datasheet, PDF (40/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Input/Output Logic Switching Characteristics
Table 60: ILOGIC Switching Characteristics
Symbol
Description
Setup/Hold
T_ICE1CK/T_ICKCE1
CE1 pin Setup/Hold with respect to CLK
T_ISRCK/T_ICKSR
SR/REV pin Setup/Hold with respect to CLK
T_IDOCK/T_IOCKD
D pin Setup/Hold with respect to CLK without Delay
T_IDOCKD/T_IOCKDD
DDLY pin Setup/Hold with respect to CLK (using IODELAY)
Combinatorial
T_IDI
T_IDID
Sequential Delays
T_IDLO
T_IDLOD
T_ICKQ
T_RQ
T_GSRQ
Set/Reset
T_RPW
D pin to O pin propagation delay, no Delay
DDLY pin to O pin propagation delay (using IODELAY)
D pin to Q1 pin using flip-flop as a latch without Delay
DDLY pin to Q1 pin using flip-flop as a latch (using IODELAY)
CLK to Q outputs
SR/REV pin to OQ/TQ out
Global Set/Reset to Q outputs
Minimum Pulse Width, SR/REV inputs
Speed Grade
-3
-2
-1
Units
0.43
0.49
0.59
ns
–0.24
–0.24
–0.24
0.85
1.00
1.22
ns
–0.20
–0.20
–0.20
0.34
0.37
0.39
ns
–0.12
–0.12
–0.12
0.31
0.33
0.36
ns
–0.09
–0.09
–0.08
0.24
0.26
0.30
ns
0.20
0.22
0.26
ns
0.44
0.50
0.58
ns
0.41
0.46
0.55
ns
0.47
0.52
0.60
ns
1.12
1.28
1.53
ns
7.30
7.30
10.10
ns
0.78
0.95
1.20 ns, Min
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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