XC5VLX110T-2FFG1738I Datasheet, PDF (81/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 97: Global Clock Setup and Hold With DCM and PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1
Units
Example Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin,⁽¹⁾ Using DCM, PLL, and Global Clock Buffer. For
situations where clock and data inputs conform to different standards, adjust the setup and hold values accordingly using the values
shown in IOB Switching Characteristics, page 32.
T_{PSDCMPLL_0}/
T_{PHDCMPLL_0}
No Delay Global Clock and IFF⁽²⁾ with DCM and XC5VLX20T
PLL in Source-Synchronous Mode
N/A
0.32
0.33
ns
0.56
0.63
XC5VLX30
0.45
0.46
0.46
ns
0.54
0.54
0.57
XC5VLX30T
0.45
0.46
0.46
ns
0.54
0.54
0.57
XC5VLX50
0.43
0.44
0.44
ns
0.56
0.56
0.59
XC5VLX50T
0.43
0.44
0.44
ns
0.56
0.56
0.59
XC5VLX85
0.40
0.42
0.42
ns
0.68
0.68
0.71
XC5VLX85T
0.39
0.42
0.42
ns
0.68
0.68
0.71
XC5VLX110
0.38
0.41
0.41
ns
0.74
0.74
0.78
XC5VLX110T
0.38
0.41
0.41
ns
0.74
0.74
0.78
XC5VLX155
0.24
0.29
0.33
ns
1.00
1.00
1.04
XC5VLX155T
0.24
0.29
0.33
ns
1.00
1.00
1.04
XC5VLX220
N/A
0.36
0.38
ns
1.23
1.27
XC5VLX220T
N/A
0.36
0.38
ns
1.23
1.27
XC5VLX330
N/A
0.34
0.37
ns
1.40
1.46
XC5VLX330T
N/A
0.36
0.38
ns
1.40
1.46
XC5VSX35T
0.44
0.46
0.46
ns
0.72
0.72
0.75
XC5VSX50T
0.41
0.43
0.43
ns
0.74
0.74
0.77
XC5VSX95T
N/A
0.41
0.41
ns
0.98
1.02
XC5VSX240T
N/A
0.35
0.38
ns
1.47
1.53
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
81