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XC5VLX110T-2FFG1738I Datasheet, PDF (51/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification
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Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Configuration Switching Characteristics
Table 70: Configuration Switching Characteristics
Symbol
Description
Power-up Timing Characteristics
TPL
TPOR
Program Latency
Power-on-Reset
TICCK
CCLK (output) delay
TPROGRAM
Program Pulse Width
Master/Slave Serial Mode Programming Switching(1)
TDCCK/TCCKD
DIN Setup/Hold, slave mode
TDSCCK/TSCCKD
DIN Setup/Hold, master mode
TCCO
FMCCK
DOUT
Maximum Frequency, master mode with
respect to nominal CCLK.
FMCCKTOL
Frequency Tolerance, master mode with
respect to nominal CCLK.
FMSCCK
Slave mode external CCLK
SelectMAP Mode Programming Switching(1)
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
TSMCSCCK/TSMCCKCS
CS_B Setup/Hold
TSMCCKW/TSMWCCK
RDWR_B Setup/Hold
TSMCKCSO
CSO_B clock to out
(330 Ω pull-up resistor required)
TSMCO
TSMCKBY
FSMCCK
CCLK to DATA out in readback
CCLK to BUSY out in readback
Maximum Frequency with respect to nominal
CCLK.
FRBCCK
Maximum Readback Frequency with respect
to nominal CCLK
FMCCKTOL
Frequency Tolerance with respect to nominal
CCLK.
Boundary-Scan Port Timing Specifications
TTAPTCK
TTCKTAP
TTCKTDO
FTCK
FTCKB
TMS and TDI Setup time before TCK
TMS and TDI Hold time after TCK
TCK falling edge to TDO output valid
Maximum configuration TCK clock frequency
Maximum boundary-scan TCK clock
frequency
Speed Grade
-3
-2
-1
3
3
3
10
10
10
50
50
50
400
400
400
250
250
250
4.0
4.0
4.0
0.0
0.0
0.0
4.0
4.0
4.0
0.0
0.0
0.0
7.5
7.5
7.5
100
100
100
±50
±50
±50
100
100
100
3.0
3.0
3.0
0.5
0.5
0.5
3.0
3.0
3.0
0.5
0.5
0.5
8.0
8.0
8.0
0.5
0.5
0.5
10
10
10
9.0
9.0
9.0
7.5
7.5
7.5
100
100
100
60
60
60
±50
±50
±50
1.0
1.0
1.0
2.0
2.0
2.0
6
6
6
66
66
66
66
66
66
Units
ms, Max
ms, Min/Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Max
MHz,
Max
%
MHz
ns, Min
ns, Min
ns, Min
ns, Min
ns, Max
ns, Max
MHz, Max
MHz, Max
%
ns, Min
ns, Min
ns, Max
MHz, Max
MHz, Max
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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