XC5VLX110T-2FFG1738I Datasheet, PDF (85/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 100: Sample Window
Symbol
T_SAMP
T_{SAMP_BUFIO}
Description
Sampling Error at Receiver Pins⁽¹⁾
Sampling Error at Receiver Pins using BUFIO⁽²⁾
Device
All
All
Speed Grade
-3
-2
-1
450
500
550
350
400
450
Units
ps
ps
Notes:
1. This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the DCM to capture the DDR input registers’ edges of operation. These measurements include:
- CLK0 DCM jitter
- DCM accuracy (phase offset)
- DCM phase shift resolution
These measurements do not include package or clock tree skew.
2. This parameter indicates the total sampling error of Virtex-5 FPGA DDR input registers across voltage, temperature, and process. The
characterization methodology uses the BUFIO clock network and IODELAY to capture the DDR input registers’ edges of operation. These
measurements do not include package or clock tree skew.
Table 101: Source-Synchronous Pin-to-Pin Setup/Hold and Clock-to-Out
Symbol
Description
Data Input Setup and Hold Times Relative to a Forwarded Clock Input Pin Using BUFIO
T_PSCS/T_PHCS
Setup/Hold of I/O clock
Pin-to-Pin Clock-to-Out Using BUFIO
T_ICKOFCS
Clock-to-Out of I/O clock
Speed Grade
-3
-2
-1
Units
–0.56 –0.54 –0.54 ns
1.59
1.72
1.91
4.42
4.82
5.40
ns
Revision History
The following table shows the revision history for this document.
Date
04/14/06
05/12/06
05/24/06
08/04/06
Version
1.0
1.1
1.2
1.3
Revision
Initial Xilinx release.
• First version posted to the Xilinx website. Minor typographical edits. Revised design software version on
page 30.
• Revised T_{IDELAYRESOLUTION} in Table 64, page 44.
• Revised TDSPCKO in Table 69, page 48.
Added register-to-register parameters to Table 52.
• Added V_DRINT, V_DRI, and C_IN values to Table 3.
• Added HSTL_I_12 and LVCMOS12 to Table 7 and renumbered the notes.
• Removed pin-to-pin performance (Table 12). Updated and added values to register-register
performance Table 52 (was Table 13).
• Added values to Table 53.
• Updated the speed specification version above Table 54.
• Added to Table 56 the I/O standards: HSTL_II_T_DCI, HSTL_II_T_DCI_18, SSTL2_II_T_DCI, and
SSTL18_II_T_DCI.
• Revised F_MAX values in Table 68, and RDWR_B Setup/Hold values in Table 70.
• In Table 74, changed F_VCOMAX, removed T_LOCKMIN, and revised T_LOCKMAX values, also removed note
pointing to Architecture Wizard.
• Removed Note 2 on Table 88.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
85