XC5VLX110T-2FFG1738I Datasheet, PDF (55/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
PLL Switching Characteristics
Table 74: PLL Specification
Symbol
Description
Speed Grade
-3
-2
-1
Units
F_INMAX
F_INMIN
F_INJITTER
F_INDUTY
Maximum Input Clock Frequency
Minimum Input Clock Frequency
Maximum Input Clock Period Jitter
Allowable Input Duty Cycle: 19—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
710
710
645
MHz
19
19
19
MHz
<20% of clock input period or 1 ns Max
25/75
%
30/70
%
Allowable Input Duty Cycle: 200—399 MHz
35/65
%
Allowable Input Duty Cycle: 400—499 MHz
40/60
%
Allowable Input Duty Cycle: >500 MHz
45/55
%
F_VCOMIN
F_VCOMAX
F_BANDWIDTH
Minimum PLL VCO Frequency
Maximum PLL VCO Frequency
Low PLL Bandwidth at Typical⁽¹⁾
High PLL Bandwidth at Typical⁽¹⁾
400
1440
1
4
400
1200
1
4
400
1000
1
4
MHz
MHz
MHz
MHz
T_STAPHAOFFSET
T_OUTJITTER
T_OUTDUTY
T_LOCKMAX
Static Phase Offset of the PLL Outputs
PLL Output Jitter⁽²⁾
PLL Output Clock Duty Cycle Precision⁽³⁾
PLL Maximum Lock Time⁽⁴⁾
PLL Maximum Output Frequency for LX20T devices
120
±150
100
N/A
120
120
Note 1
±200
±200
100
100
667
600
ps
ps
µs
MHz
PLL Maximum Output Frequency for LX30, LX30T, LX50,
710
667
600
MHz
LX50T, LX85, LX85T, LX110, LX110T, SX35T, SX50T, FX30T,
and FX70Tdevices
F_OUTMAX
PLL Maximum Output Frequency for LX155, LX155T, and
FX100T devices
650
600
550
MHz
PLL Maximum Output Frequency for FX130T devices
550
500
450
MHz
F_OUTMIN
T_EXTFDVAR
RST_MINPULSE
F_PFDMAX
F_PFDMIN
T_FBDELAY
PLL Maximum Output Frequency for LX220, LX220T, LX330,
LX330T, SX95T, SX240T, TX150T, TX240T, and FX200T
devices
PLL Minimum Output Frequency⁽⁵⁾
External Clock Feedback Variation
Minimum Reset Pulse Width
Maximum Frequency at the Phase Frequency Detector
Minimum Frequency at the Phase Frequency Detector
Maximum External Delay in the Feedback Path
N/A
500
450
MHz
3.125 3.125 3.125 MHz
< 20% of clock input period or 1 ns Max
5
5
5
ns
550
500
450
MHz
19
19
19
MHz
3 ns Max or one CLKIN cycle
Notes:
1. The PLL does not filter typical spread spectrum input clocks because they are usually far below the bandwidth filter frequencies.
2. Values for this parameter are available in the Architecture Wizard.
3. Includes global clock buffer.
4. The LOCK signal must be sampled after T_LOCKMAX. The LOCK signal is invalid after configuration or reset until the T_LOCKMAX time has
expired.
5. Calculated as F_VCO/128 assuming output duty cycle is 50%.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
55