XC5VLX110T-2FFG1738I Datasheet, PDF (89/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Date
06/26/07
07/26/07
09/27/07
11/05/07
12/11/07
02/05/08
Version
3.3
3.4
3.5
3.6
3.7
3.8
Revision
• Added conditions to DV_PPIN in Table 28, page 14.
• Changed the F_GTXMAX symbol name to F_GTPMAX.
• Updated GTP maximum line rates to 3.75 Gb/s in Table 30, page 16.
• Updated maximum frequencies in Table 33, page 17.
• Added 3.75 Gb/s condition and changed maximum value of F_GTX in Table 34, page 17.
• Added 3.75 Gb/s sinusoidal jitter specification and changed maximum value of F_GRX in Table 35,
page 18.
• Changed analog input common mode ranges in Table 51, page 26.
• Changed T_PKGSKEW values in Table 99, page 84.
• Added maximum value of I_REF to Table 3, page 2.
• Revised Table 54 and changed the design software version in Table 55 for production devices.
• In Table 64, page 44, added High Performance Mode to Note 2.
• In Table 70, page 51, revised description of T_SMDCCK/T_SMCCKD.
• Added Note 4 to T_{DUTYCYCRANGE_200_400} frequency range in Table 78, page 59.
• In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 91 through Table 96.
• Added I_BATT value and Note 2 to Table 3.
• Added DRP Clock Frequency and Note 4 to Table 51. Revised the typical and maximum values and
units for gain error and bipolar gain error.
• Removed unsupported XC5VSX95T -3 speed grade from Table 54 and Table 55.
• Removed unsupported I/O standards (LVDS_33, LVDSEXT_33, and ULVDS_25) from Table 51. Also
updated LVDSEXT, 2.5V in Table 59.
• Added values to Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK in
Table 70.
• In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised note 1 in Table 91 through Table 97.
• Removed note 1 from Table 52, page 28. F_MAX of clock is not an applicable limitation.
• Revised DDR2 memory interface performance in Table 53, page 29.
• Revised Table 55 to add ISE 9.2i SP3 where applicable.
• Removed XC5VSX95T -3 speed grade support from applicable tables.
• Removed unsupported I/O standard (LVPECL_33) from Table 58 and added LVPECL_25.
• Added T_SMCO and T_SMCKBY to Table 70, page 51.
• Revised note 3 in Table 76, page 57 and Table 77, page 58.
• Clarified notes in Table 87 to Table 90, and Table 94 to Table 97.
• Revised note 1 in Table 99.
• Added new devices (XC5VLX20T, XC5VLX155, and XC5VLX155T) throughout document.
• Removed -3 speed grade from XC5VSX95T device lists.
• Added Table 31, page 16.
• Revised Virtex-5 Device Pin-to-Pin Output Parameter Guidelines in Table 87 through Table 90, and
Virtex-5 Device Pin-to-Pin Input Parameter Guidelines in Table 90 and Table 92 through Table 97. Also
revised Note 1 on Table 92 through Table 97.
• Revised Note 1 on Table 99.
• Updated date on version 3.7. Other minor typographical edits.
• Updated the sentence: Xilinx does not specify the current or I/O behavior for other power-on sequences,
on page 6.
• Added values and notes to Table 27, page 14. Removed I_CCINTQ since it is included in Table 4, page 3.
Combined I_VTTRXCQ into I_VTTRXQ values.
• Revised T_LLSKEW values in Table 34, page 17.
• Revised R_XPPMTOL values and note 1 in Table 35, page 18.
• Revised -2 performance value for SPI-4.2 in Table 53, page 29.
• Added T_{IODDO_T}, T_{IODDO_IDATAIN}, T_{IODDO_ODATAIN}, and Note 3 to Table 64, page 44.
• Split out the F_MAX rows in Table 71 and the F_OUTMAX rows in Table 74, revised -2 value for smallest
devices in both tables.
• Added Table 75: PLL in PMCD Mode Switching Characteristics, page 56.
• Updated Table 4 and Table 84 to Table 98 to match speed grade designations listed in Table 54.
• Revised Note 1 on Table 96 and Table 97.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
89