XC5VLX110T-2FFG1738I Datasheet, PDF (28/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in
Virtex-5 devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are
subject to the same guidelines as the Switching Characteristics, page 30. Table 52 shows internal (register-to-register)
performance.
Table 52: Register-to-Register Performance
Description
Basic Functions
16:1 Multiplexer
32:1 Multiplexer
64:1 Multiplexer
9 x 9 Logic Multiplier with 4 pipe stages
9 x 9 Logic Multiplier with 5 pipe stages
16-bit Adder
32-bit Adder
64-bit Adder
Register to LUT to Register
16-bit Counter
32-bit Counter
64-bit Counter
Memory
Cascaded block RAM (64K)
Block RAM Pipelined
Single-Port 512 x 36 bits
Single-Port 4096 x 4 bits
Dual-Port A: 4096 x 4 bits and B: 1024 x 18 bits
Distributed RAM
Single-Port 16 x 8
Single-Port 32 x 8
Single-Port 64 x 8
Dual-Port 16 x 8
Shift Register Chain
16-bit
32-bit
64-bit
Register-to-Register (with I/O Delays)
Speed Grade
-3
-2
-1
550
500
450
550
500
450
511
467
407
468
438
428
550
500
428
550
500
450
550
500
447
423
377
323
550
500
450
550
500
450
550
500
450
428
381
333
500
450
400
550
500
450
550
500
450
550
500
450
550
500
450
550
500
450
550
500
450
550
500
450
550
500
450
550
500
438
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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