XC5VLX110T-2FFG1738I Datasheet, PDF (21/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

X-Ref Target - Figure 7
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0
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DV_PPOUT
–V
P–N
Figure 7: Peak-to-Peak Differential Output Voltage
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Table 41 summarizes the DC specifications of the clock input of the GTX_DUAL tile. Figure 8 shows the single-ended input
voltage swing. Figure 9 shows the peak-to-peak differential clock input voltage swing. Consult UG198: Virtex-5 FPGA
RocketIO GTX Transceiver User Guide for further details.
Table 41: GTX_DUAL Tile Clock DC Input Level Specification⁽¹⁾
Symbol
DC Parameter
Conditions
V_IDIFF
V_ISE
R_IN
C_EXT
Differential peak-to-peak input voltage
Single-ended input voltage
Differential input resistance
Required external AC coupling capacitor
Notes:
1. V_MIN = 0V and V_MAX = 1200mV
Min Typ
210 800
105 400
90
105
100
Max
2000
1000
130
Units
mV
mV
Ω
nF
X-Ref Target - Figure 8
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P
N
0
X-Ref Target - Figure 9
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Figure 8: Single-Ended Clock Input Voltage Swing Peak-to-Peak
P–N
V_ISE
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0
V_IDIFF
–V
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Figure 9: Differential Clock Input Voltage Swing Peak-to-Peak
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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