XC5VLX110T-2FFG1738I Datasheet, PDF (25/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 47: GTX_DUAL Tile Receiver Switching Characteristics (Cont’d)
Symbol
JT_SJ₇₅₀
Sinusoidal Jitter⁽⁴⁾⁽⁶⁾
JT_SJ₁₅₀
Sinusoidal Jitter⁽⁴⁾⁽⁶⁾
SJ Jitter Tolerance with Stressed Eye⁽³⁾
Description
750 Mb/s
150 Mb/s
JT_TJSE_4.25
Total Jitter with Stressed
Eye⁽⁷⁾
4.25 Gb/s
JT_SJSE_4.25
Sinusoidal Jitter with
Stressed Eye⁽⁷⁾
4.25 Gb/s
Min
Typ
0.57
0.57
0.69
0.1
Max
Units
UI
UI
UI
UI
Notes:
1. Using PLL_RXDIVSEL_OUT = 1, 2, and 4.
2. Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3. All jitter values are based on a Bit Error Ratio of 1e^–12.
4. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
5. PLL frequency at 1.6 GHz and OUTDIV = 1.
6. GREFCLK can be used for serial data rates up to 1.0 Gb/s, but performance is not guaranteed.
7. Composite jitter with RX equalizer enabled. DFE disabled.
CRC Block Switching Characteristics
Table 48: CRC Block Switching Characteristics
Symbol
Description
F_CRC
CRCCLK maximum frequency
Speed Grade
-3
-2
-1
325
325
270
Ethernet MAC Switching Characteristics
Consult UG194: Virtex-5 FPGA Tri-mode Ethernet Media Access Controller User Guide for further information.
Table 49: Maximum Ethernet MAC Performance
Symbol
Description
F_TEMACCLIENT Client interface maximum frequency
F_TEMACPHY
Physical interface maximum frequency
Conditions
10 Mb/s – 8-bit width
100 Mb/s – 8-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 16-bit width
10 Mb/s – 4-bit width
100 Mb/s – 4-bit width
1000 Mb/s – 8-bit width
2000 Mb/s – 8-bit width
Speed Grade
-3
-2
-1
1.25
1.25
1.25
12.5
12.5
12.5
125
125
125
125
125
125
2.5
2.5
2.5
25
25
25
125
125
125
250
250
250
Units
MHz
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Endpoint Block for PCI Express Designs Switching Characteristics
Consult UG197: Virtex-5 FPGA Integrated Endpoint Block for PCI Express Designs User Guide for further information.
Table 50: Maximum Performance for PCI Express Designs
Symbol
Description
F_PCIECORE
F_PCIEUSER
Core clock maximum frequency
User clock maximum frequency
Speed Grade
-3
-2
-1
250
250
250
250
250
250
Units
MHz
MHz
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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