XC5VLX110T-2FFG1738I Datasheet, PDF (61/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 81: Miscellaneous Timing Parameters
Symbol
Description
Speed Grade
-3
-2
-1
Units
Time Required to Achieve LOCK
T_{DLL_240}
T_{DLL_120_240}
T_{DLL_60_120}
T_{DLL_50_60}
T_{DLL_40_50}
T_{DLL_30_40}
T_{DLL_24_30}
T_{DLL_30}
T_{FX_MIN}
DLL output – Frequency range > 240 MHz ⁽¹⁾
DLL output – Frequency range 120 - 240 MHz ⁽¹⁾
DLL output – Frequency range 60 - 120 MHz ⁽¹⁾
DLL output – Frequency range 50 - 60 MHz⁽¹⁾
DLL output – Frequency range 40 - 50 MHz ⁽¹⁾
DLL output – Frequency range 30 - 40 MHz ⁽¹⁾
DLL output – Frequency range 24 - 30 MHz⁽¹⁾
DLL output – Frequency range < 30 MHz ⁽¹⁾
DFS outputs⁽²⁾
T_{FX_MAX}
T_{DLL_FINE_SHIFT}
Multiplication factor for DLL lock time with Fine Shift
Fine Phase Shifting
80.00 80.00 80.00
µs
250.00 250.00 250.00 µs
900.00 900.00 900.00 µs
1300.00 1300.00 1300.00 µs
2000.00 2000.00 2000.00 µs
3600.00 3600.00 3600.00 µs
5000.00 5000.00 5000.00 µs
5000.00 5000.00 5000.00 µs
10.00 10.00 10.00 ms
10.00 10.00 10.00 ms
2.00
2.00
2.00
T_{RANGE_MS}
T_{RANGE_MR}
Delay Lines
Absolute shifting range in maximum speed mode
Absolute shifting range in maximum range mode
7.00
7.00
7.00
ns
10.00 10.00 10.00
ns
T_{TAP_MS_MIN}
T_{TAP_MS_MAX}
T_{TAP_MR_MIN}
T_{TAP_MR_MAX}
Tap delay resolution (Min) in maximum speed mode
Tap delay resolution (Max) in maximum speed mode
Tap delay resolution (Min) in maximum range mode
Tap delay resolution (Max) in maximum range mode
7.00
7.00
7.00
ps
30.00 30.00 30.00
ps
10.00 10.00 10.00
ps
40.00 40.00 40.00
ps
Notes:
1. DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
2. DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
Table 82: Frequency Synthesis
Attribute
CLKFX_MULTIPLY
CLKFX_DIVIDE
Min
Max
2
33
1
32
Table 83: DCM Switching Characteristics
Symbol
Description
T_{DMCCK_PSEN}/ T_{DMCKC_PSEN}
PSEN Setup/Hold
T_{DMCCK_PSINCDEC}/ T_{DMCKC_PSINCDEC}
T_{DMCKO_PSDONE}
PSINCDEC Setup/Hold
Clock to out of PSDONE
Speed Grade
-3
-2
-1
1.20
1.35
1.56
0.00
0.00
0.00
1.20
1.35
1.56
0.00
0.00
0.00
1.00
1.12
1.30
Units
ns
ns
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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