XC5VLX110T-2FFG1738I Datasheet, PDF (77/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 95: Global Clock Setup and Hold With PLL in Source-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.⁽¹⁾
T_PSPLL0/ T_PHPLL0 No Delay Global Clock and IFF⁽²⁾ with PLL in
Source-Synchronous Mode
XC5VLX20T
N/A
–0.26 –0.25
1.21
1.40
XC5VLX30
–0.33
1.13
–0.33
1.22
–0.33
1.34
XC5VLX30T
–0.33
1.13
–0.33
1.22
–0.33
1.34
XC5VLX50
–0.24
1.21
–0.24
1.30
–0.23
1.42
XC5VLX50T
–0.24
1.21
–0.24
1.30
–0.23
1.42
XC5VLX85
–0.25
1.23
–0.23
1.30
–0.22
1.39
XC5VLX85T
–0.25
1.23
–0.23
1.30
–0.22
1.39
XC5VLX110
–0.26
1.27
–0.24
1.34
–0.23
1.43
XC5VLX110T
–0.26
1.27
–0.25
1.34
–0.23
1.43
XC5VLX155
–0.15
1.48
–0.12
1.56
–0.10
1.67
XC5VLX155T
–0.16
1.48
–0.12
1.56
–0.10
1.67
XC5VLX220
N/A
–0.34 –0.30
1.75
1.80
XC5VLX220T
N/A
–0.34 –0.31
1.75
1.80
XC5VLX330
N/A
–0.34 –0.30
1.90
1.95
XC5VLX330T
N/A
–0.34 –0.30
1.90
1.95
XC5VSX35T
–0.19
1.36
–0.18
1.44
–0.16
1.54
XC5VSX50T
–0.27
1.37
–0.26
1.44
–0.25
1.53
XC5VSX95T
N/A
–0.26 –0.24
1.58
1.65
XC5VSX240T
N/A
–0.35 –0.31
1.97
2.02
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
77