XC5VLX110T-2FFG1738I Datasheet, PDF (62/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Virtex-5 Device Pin-to-Pin Output Parameter Guidelines
All devices are 100% functionally tested. The representative values for typical pin locations and normal clock loading are
listed in Table 84. Values are expressed in nanoseconds unless otherwise noted.
Table 84: Global Clock Input to Output Delay Without DCM or PLL
Symbol
Description
Device
Speed Grade
-3
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, without DCM or PLL
T_ICKOF
Global Clock and OUTFF without DCM or PLL
XC5VLX20T
XC5VLX30
N/A
5.98
6.69
5.54
6.04
6.73
XC5VLX30T
5.54
6.04
6.73
XC5VLX50
5.59
6.09
6.79
XC5VLX50T
5.59
6.09
6.79
XC5VLX85
5.78
6.28
6.99
XC5VLX85T
5.78
6.28
6.99
XC5VLX110
5.84
6.35
7.06
XC5VLX110T
5.84
6.35
7.06
XC5VLX155
6.16
6.68
7.52
XC5VLX155T
6.16
6.68
7.52
XC5VLX220
N/A
6.99
7.71
XC5VLX220T
N/A
6.99
7.71
XC5VLX330
N/A
7.17
7.91
XC5VLX330T
N/A
7.17
7.91
XC5VSX35T
5.72
6.22
6.92
XC5VSX50T
5.77
6.27
6.97
XC5VSX95T
N/A
6.59
7.30
XC5VSX240T
N/A
7.24
7.98
XC5VTX150T
N/A
6.58
7.30
XC5VTX240T
N/A
6.88
7.61
XC5VFX30T
5.73
6.21
6.89
XC5VFX70T
5.82
6.33
7.04
XC5VFX100T
6.21
6.73
7.44
XC5VFX130T
6.28
6.80
7.52
XC5VFX200T
N/A
7.17
7.91
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
62