XC5VLX110T-2FFG1738I Datasheet, PDF (56/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 75: PLL in PMCD Mode Switching Characteristics
Symbol
Description
T_{PLLCCK_REL}/T_{PLLCKC_REL}
REL Setup and Hold for all Outputs
T_PLLCCKO
CLKIN_FREQ_MAX
CLKIN_FREQ_MIN
CLKIN_DUTY_CYCLE
RES_REL_PULSE_MIN
Maximum Clock Propagation Delay
Maximum Input Frequency
Minimum Input Frequency
Allowable Input Duty Cycle: 1—49 MHz
Allowable Input Duty Cycle: 50—199 MHz
Allowable Input Duty Cycle: 200—399 MHz
Allowable Input Duty Cycle: 400—499 MHz
Allowable Input Duty Cycle: >500 MHz
Minimum Pulse Width for RST and REL
Speed Grade
-3
-2
-1
0.00
0.00
0.00
0.60
0.60
0.60
4.6
4.6
5.2
710
710
645
1
1
1
25/75
30/70
35/65
40/60
45/55
5
5
5
Units
ns
ns
MHz
MHz
%
%
%
%
%
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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