XC5VLX110T-2FFG1738I Datasheet, PDF (87/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Date
02/02/07
Version
3.0
Revision
• Added XC5VSX35T, XC5VSX50T, and SX5VSX95T devices to appropriate tables.
• Revised the I_RPU values in Table 3, page 2.
• Revised the I_CCAUXQ values in Table 4, page 3.
• Added values to Table 5, page 6.
• Minor added notes and changed descriptions in Table 25, page 13 and Table 26, page 13.
• Revised the SFI-4.1 (SDR LVDS Interface) -1 values in Table 53, page 29.
• Revised gain error, bipolar gain error, and event conversion time in Table 51, page 26
• Changed the design software version that matches this data sheet above Table 54 on page 30.
• In Switching Characteristics, the following values are revised:
• LVCMOS25, Fast, 12 mA in Table 56, page 32.
• Setup and Hold and T_ICKQ in Table 60, page 40.
• T_OCKQ in Table 61, page 41.
• Sequential delay values in Table 63, page 43.
• T_CXB, T_CEO, and T_DICK in Table 65, page 44.
• T_{RCKO_DO}, T_{RCKO_POINTERS}, T_{RCKO_ECCR}, T_{RCKO_ECC}, T_{RCCK_ADDR}, T_{RDCK_DI}, T_{RDCK_DI_ECC},
T_{RCCK_WREN}, and T_{RCO_FLAGS} in Table 68, page 47.
• T_{DSPDCK_CC}, T_{DSPCCK_{RSTAA, RSTBB}}, T_{DSPCKO_{PP, CRYOUTP}}, F_{MAX_MULT_NOMREG} and
F_{MAX_MULT_NOMREG_PATDET} in Table 69, page 48.
• T_{BCCKO_O}, and T_{BGCKO_O} in Table 71, page 53.
• T_{BUFIOCKO_O} and F_MAX in Table 72, page 53.
• T_{BRCKO_O} and T_{BRCKO_O_BYP} in Table 73, page 54.
• Parameters in Table 74, page 55 including notes.
• In Virtex-5 Device Pin-to-Pin Output Parameter Guidelines:
• Revised values in Table 84, Table 85, and Table 86.
• In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines:
• Clarified description in Table 91, page 69.
• Revised values in Table 91, Table 92, and Table 93.
• Removed duplicate T_{BUFR_MAX_FREQ} and T_{BUFIO_MAX_FREQ} from Table 98.
• Revised values in Table 101, page 85.
DS202 (v5.3) May 5, 2010
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Product Specification
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