XC5VLX110T-2FFG1738I Datasheet, PDF (88/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Date
05/18/07
06/15/07
Version
3.1
3.2
Revision
• Added typical values for n and r in Table 3.
• Revised and added values to Table 4.
• Revised standard I/O levels in Table 7.
• Additions and updates to Table 26, Table 28, Table 29, Table 30, Table 48, Table 32, Table 33, Table 34,
and Table 35.
• Added Ethernet MAC Switching Characteristics, page 25.
• Changed the design software version that matches this data sheet above Table 54 on page 30.
• Added new section: I/O Standard Adjustment Measurement Methodology, page 37.
• In Switching Characteristics, the following values are revised:
• LVTTL, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 56).
• LVCMOS33, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 56).
• LVCMOS25, Slow and Fast, 2 mA and 4 mA, and Fast 12 mA (Table 56).
• LVCMOS18, Slow and Fast, 2 mA, 4 mA, and 6 mA (Table 56).
• LVCMOS15 and LVCMOS12, Slow and Fast, 2 mA (Table 56).
• T_IDOCK and T_IDOCKD in Table 60.
• Setup/Hold for Control Lines and Data Lines in Table 62.
• Add T_{IDELAYPAT_JIT} and revised T_{IDELAYRESOLUTION} in Table 64, page 44 and added Notes 1 and 2.
• Revised T_RCK page 45 and removed T_CKSR Table 65, page 44.
• Replaced T_TWC with T_MCP symbol in Table 66, page 46.
• Revised T_CECK in Table 67.
• Revised T_{RCKO_FLAGS} and T_{RDCK_DI_ECC} encode only in Table 68.
• Revised Hold Times of Data/Control Pins to the Input Register Clock.
Setup/Hold times of {PCIN, CARRYCASCIN, MULTSIGNIN} input to P register CLK. Hold times of
some of the CE pins. Hold times of some of the RST pins. Hold times of {A, B} input to {P,
CARRYOUT} output using multiplier and {ACIN, BCIN} input to {P, CARRYOUT} output using
multiplier, CLK (AREG, BREG) to {P, CARRYOUT} output using multiplier, in Table 69.
• Updated and added values to Table 70, page 51.
• Revised -1 speed F_MAX value in Table 72, page 53.
• Added Note 4 to T_LOCKMAX and revised F_INDUTY, F_INMAX,and F_VCOMAX in Table 74, page 55.
• Added ± values to Table 79 and Table 80. Changed T_{OUT_OFFSET} in Table 80.
• In Virtex-5 Device Pin-to-Pin Output Parameter Guidelines:
• Revised values in Table 84 through Table 90.
• In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines:
• Revised values in Table 91 through Table 97.
• In Source-Synchronous Switching Characteristics:
• Revised values in Table 98, page 83.
• Added package skew values to Table 99, page 84.
• Revised values in Table 101, page 85.
• Updated T_STG in Table 1.
• Corrected V_OH/V_OL in Table 9 and Table 10, page 8.
• Changed the design software version that matches this data sheet above Table 54 on page 30.
• Added Production Silicon and ISE Software Status, page 31.
• Added T_{IODELAY_CLK_MAX} and revised T_CKSR in Table 64, page 44.
• In Virtex-5 Device Pin-to-Pin Output Parameter Guidelines: Revised values in Table 85 through
Table 90.
• In Virtex-5 Device Pin-to-Pin Input Parameter Guidelines: Revised values in Table 92 through Table 97.
• Corrected units to ns in Table 98, page 83.
DS202 (v5.3) May 5, 2010
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Product Specification
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