XC5VLX110T-2FFG1738I Datasheet, PDF (52/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 70: Configuration Switching Characteristics (Cont’d)
Symbol
Description
Speed Grade
-3
-2
-1
BPI Master Flash Mode Programming Switching
T_BPICCO(4)
ADDR[25:0], RS[1:0], FCS_B, FOE_B,
10
10
10
FWE_B outputs valid after CCLK rising edge
T_BPIDCC/T_BPICCD
Setup/Hold on D[15:0] data input pins
3.0
3.0
3.0
0.5
0.5
0.5
T_INITADDR
Minimum period of initial ADDR[25:0] address 3.0
3.0
3.0
cycles
SPI Master Flash Mode Programming Switching
T_SPIDCC/T_SPIDCCD
DIN Setup/Hold before/after the rising CCLK 4.0
4.0
4.0
edge
0.0
0.0
0.0
T_SPICCM
MOSI clock to out
10
10
10
T_SPICCFC
FCS_B clock to out
10
10
10
T_FSINIT/T_FSINITH
FS[2:0] to INIT_B rising edge Setup and Hold 2
2
2
CCLK Output (Master Modes)
T_MCCKL
T_MCCKH
CCLK Input (Slave Modes)
Master CCLK clock minimum Low time
Master CCLK clock minimum High time
3.0
3.0
3.0
3.0
3.0
3.0
T_SCCKL
Slave CCLK clock minimum Low time
2.0
2.0
2.0
T_SCCKH
Slave CCLK clock minimum High time
2.0
2.0
2.0
Dynamic Reconfiguration Port (DRP) for DCM and PLL Before and After DCLK
F_DCK
T_{DMCCK_DADDR}/T_{DMCKC_DADDR}
Maximum frequency for DCLK
DADDR Setup/Hold
500
450
400
1.2
1.35
1.56
0.0
0.0
0.0
T_{DMCCK_DI}/T_{DMCKC_DI}
DI Setup/Hold
1.2
1.35
1.56
0.0
0.0
0.0
T_{DMCCK_DEN}/T_{DMCKC_DEN}
DEN Setup/Hold time
1.2
1.35
1.56
0.0
0.0
0.0
T_{DMCCK_DWE}/T_{DMCKC_DWE}
T_{DMCKO_DO}
T_{DMCKO_DRDY}
DWE Setup/Hold time
CLK to out of DO⁽³⁾
CLK to out of DRDY
1.2
1.35
1.56
0.0
0.0
0.0
1.0
1.12
1.3
1.0
1.12
1.3
Notes:
1. Maximum frequency and setup/hold timing parameters are for 3.3V and 2.5V configuration voltages.
2. To support longer delays in configuration, use the design solutions described in UG190: Virtex-5 FPGA User Guide.
3. DO will hold until next DRP operation.
4. Only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the I/O.
Units
ns
ns
CCLK cycles
ns
ns
ns
µs
ns, Min
ns, Min
ns, Min
ns, Min
MHz
ns
ns
ns
ns
ns
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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