XC5VLX110T-2FFG1738I Datasheet, PDF (63/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 85: Global Clock Input to Output Delay With DCM in System-Synchronous Mode
Symbol
Description
Device
Speed Grade
-3
-2
-1
LVCMOS25 Global Clock Input to Output Delay using Output Flip-Flop, 12mA, Fast Slew Rate, with DCM
in System-Synchronous Mode
T_ICKOFDCM
Global Clock and OUTFF with DCM
XC5VLX20T
XC5VLX30
N/A
2.53
2.93
2.33
2.56
2.93
XC5VLX30T
2.33
2.56
2.93
XC5VLX50
2.35
2.58
2.95
XC5VLX50T
2.35
2.58
2.95
XC5VLX85
2.41
2.63
3.00
XC5VLX85T
2.41
2.63
3.00
XC5VLX110
2.46
2.69
3.06
XC5VLX110T
2.46
2.69
3.06
XC5VLX155
2.51
2.74
3.10
XC5VLX155T
2.51
2.74
3.10
XC5VLX220
N/A
2.83
3.18
XC5VLX220T
N/A
2.83
3.18
XC5VLX330
N/A
3.00
3.37
XC5VLX330T
N/A
3.00
3.37
XC5VSX35T
2.44
2.67
3.03
XC5VSX50T
2.46
2.69
3.05
XC5VSX95T
N/A
2.64
3.00
XC5VSX240T
N/A
3.00
3.36
XC5VTX150T
N/A
2.77
3.15
XC5VTX240T
N/A
2.78
3.15
XC5VFX30T
2.55
2.82
3.20
XC5VFX70T
2.48
2.74
3.12
XC5VFX100T
2.33
2.59
3.00
XC5VFX130T
2.40
2.67
3.07
XC5VFX200T
N/A
2.87
3.27
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all
accessible IOB and CLB flip-flops are clocked by the global clock net.
2. DCM output jitter is already included in the timing calculation.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
63