XC5VLX110T-2FFG1738I Datasheet, PDF (86/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Date
09/06/06
10/13/06
01/05/07
Version
2.0
2.1
2.2
Revision
• Added new sections for LXT devices and added LXT devices to the appropriate tables. The addition of
the GTP_DUAL Tile Specifications required the tables to be renumbered.
• Changed maximum V_IN values in Table 1 and Table 2.
• Updated values and added T_j = 85°C to Table 4, page 3.
• Revised the cascade block RAM Memory, page 28 section in Table 52 to 64K with new I/O delays.
• Revised the setup and hold times in Table 60, page 40.
• Added F_{MAX_CASCADE} to Table 68, page 47.
• Revised F_FXLFMSMAX and F_{CLKINLFFXMSMAX} in Table 76, page 57.
• Added System Monitor parameters. Added XC5VLX85T to appropriate tables.
• Revised Table 28 including notes. Added Table 29, and Figure 3 and Figure 4.
• Added Table 48, page 25: RocketIO CRC block.
• Revised design software version and Table 54 on page 30.
• Updated ILOGIC Switching Characteristics, page 40
• Updated F_{MAX_ECC} in Table 68, page 47.
• Changed hold times for T_SMDCCK/ T_SMCCKD and T_BPIDCC/T_BPICCD in Table 70, page 51.
• Revised T_FBDELAY, F_OUTMIN, F_OUTMAX, and F_INJITTER Table 74, page 55.
• Revised Table 76, page 57.
• Added I_IN to Table 2. Added XC5VLX220T to appropriate tables.
• Added LVDCI33, LVDCI25, LVDCI18, LVDCI15 to Table 7.
• Update the symbols in the GTP Transceiver Table 24, Table 25, and Table 26.
• Add values for -1 speed grade in Table 30, page 16.
• Added SFI-4.1 values to Table 53, page 29.
• Removed -3 speed grade from available LX220 device list in Table 54, page 30.
• Added maximum frequency to Table 72 and Table 73, page 54.
• In Table 76, page 57 changed the all the CLKDV, CLKFX, and CLKFX180 Min values and the CLKIN
Min values in the Input Clocks (High Frequency Mode) section.
• Added values to Table 79 and Table 80, page 60.
DS202 (v5.3) May 5, 2010
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Product Specification
86