XC5VLX110T-2FFG1738I Datasheet, PDF(37/91 Page) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

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XC5VLX110T-2FFG1738I Datasheet, PDF (37/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

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Virtex-5 FPGA Data Sheet: DC and Switching Characteristics

I/O Standard Adjustment Measurement Methodology

Input Delay Measurements

Table 58 shows the test setup parameters used for measuring input delay.

Table 58: Input Delay Measurement Methodology

Description

I/O Standard Attribute

LVTTL (Low-Voltage Transistor-Transistor Logic) LVTTL

LVCMOS (Low-Voltage CMOS), 3.3V

LVCMOS33

LVCMOS, 2.5V

LVCMOS25

LVCMOS, 1.8V

LVCMOS18

LVCMOS, 1.5V

LVCMOS15

LVCMOS, 1.2V

LVCMOS12

PCI (Peripheral Component Interconnect),

33 MHz, 3.3V

PCI33_3

PCI, 66 MHz, 3.3V

PCI66_3

PCI-X, 133 MHz, 3.3V

PCIX

GTL (Gunning Transceiver Logic)

GTL

GTL Plus

GTLP

HSTL (High-Speed Transceiver Logic),

Class I & II

HSTL_I, HSTL_II

HSTL, Class III & IV

HSTL_III, HSTL_IV

HSTL, Class I & II, 1.8V

HSTL_I_18, HSTL_II_18

HSTL, Class III & IV, 1.8V

HSTL_III_18, HSTL_IV_18

SSTL (Stub Terminated Transceiver Logic),

Class I & II, 3.3V

SSTL3_I, SSTL3_II

SSTL, Class I & II, 2.5V

SSTL2_I, SSTL2_II

SSTL, Class I & II, 1.8V

SSTL18_I, SSTL18_II

AGP-2X/AGP (Accelerated Graphics Port)

AGP

LVDS (Low-Voltage Differential Signaling), 2.5V LVDS_25

LVDSEXT (LVDS Extended Mode), 2.5V

LVDSEXT_25

LDT (HyperTransport), 2.5V

LDT_25

LVPECL (Low-Voltage Positive Emitter-Coupled LVPECL_25

Logic), 2.5V

VL (1,2)

VH (1,2)

3.0

3.3

2.5

1.8

1.5

1.2

Per PCIâ¢ Specification

VMEAS(1,4,5)

1.4

1.65

1.25

0.9

0.75

0.6

VREF(1,3,5)

Per PCI Specification

Per PCI-Xâ¢ Specification

VREF â 0.2

VREF â 0.5

VREF + 0.2

VREF + 0.5

VREF â 0.5

VREF â 1.00

VREF + 0.5

VREF + 1.00

VREF â 0.75

VREF + 0.75

VREF â 0.5

VREF + 0.5

VREF â (0.2 xVCCO) VREF + (0.2 xVCCO)

1.2 â 0.125

1.2 + 0.125

1.2 â 0.125

1.2 + 0.125

0.6 â 0.125

0.6 + 0.125

1.15 â 0.3

VREF

0(6)

0.80

1.0

0.75

0.90

1.08

1.5

1.25

0.90

AGP Spec

Notes:

1. The input delay measurement methodology parameters for LVDCI are the same for LVCMOS standards of the same voltage. Input delay

measurement methodology parameters for HSLVDCI are the same as for HSTL_II standards of the same voltage. Parameters for all other DCI

standards are the same for the corresponding non-DCI standards.

2. Input waveform switches between VLand VH.

3. Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values

listed are typical.

4. Input voltage level from which measurement starts.

5. This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 11.

6. The value given is the differential input voltage.

DS202 (v5.3) May 5, 2010

www.xilinx.com

Product Specification

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