XC5VLX110T-2FFG1738I Datasheet, PDF (18/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 35: GTP_DUAL Tile Receiver Switching Characteristics
Symbol
Description
Min
Typ
Max Units
F_GTPRX
Serial data rate
RX oversampler not enabled
0.5
RX oversampler enabled
0.1
F_GTPMAX
0.5
Gb/s
Gb/s
R_XOOBVDPP
OOB detect threshold
peak-to-peak
OOBDETECT_THRESHOLD = 100
60
105
165
mV
R_XSST
Receiver spread-spectrum
tracking⁽¹⁾
Modulated @ 33 KHz
–5000
0
ppm
R_XRL
Run length (CID)
R_XPPMTOL
Data/REFCLK PPM offset
tolerance⁽²⁾
SJ Jitter Tolerance⁽⁴⁾
JT_SJ_3.75
Sinusoidal Jitter⁽⁵⁾
JT_SJ_3.2
Sinusoidal Jitter⁽⁵⁾
JT_SJ_2.50
Sinusoidal Jitter⁽⁵⁾
JT_SJ_2.00
Sinusoidal Jitter⁽⁵⁾
JT_SJ_1.00
Sinusoidal Jitter⁽⁵⁾
JT_SJ₅₀₀
Sinusoidal Jitter⁽⁵⁾
JT_SJ₅₀₀
Sinusoidal Jitter⁽⁵⁾
JT_SJ₁₀₀
Sinusoidal Jitter⁽⁵⁾
SJ Jitter Tolerance with Stressed Eye⁽⁴⁾
Internal AC capacitor bypassed
CDR 2^nd-order loop disabled with
PLL_RXDIVSEL_OUT = 1⁽³⁾
CDR 2^nd-order loop disabled with
PLL_RXDIVSEL_OUT = 2⁽³⁾
CDR 2^nd-order loop disabled with
PLL_RXDIVSEL_OUT = 4⁽³⁾
CDR 2^nd-order loop enabled
3.75 Gb/s
3.20 Gb/s
2.50 Gb/s
2.00 Gb/s
1.00 Gb/s
500 Mb/s
500 Mb/s OS
100 Mb/s OS
–200
–200
–100
–1000
0.30
0.40
0.40
0.40
0.30
0.30
0.30
0.30
150
UI
200
ppm
200
ppm
100
ppm
1000 ppm
UI
UI
UI
UI
UI
UI
UI
UI
JT_TJSE_3.2
Total Jitter with Stressed
Eye⁽⁶⁾
3.20 Gb/s
0.87
UI
JT_SJSE_3.2
Sinusoidal Jitter with
Stressed Eye⁽⁶⁾
3.20 Gb/s
0.30
UI
Notes:
1. Using PLL_RXDIVSEL_OUT = 1 only.
2. Indicates the maximum offset between the receiver reference clock and the serial data. For example, a reference clock with ±100 ppm
resolution results in a maximum offset of 200 ppm between the reference clock and the serial data.
3. CDR 1st-order step size set to 2.
4. All jitter values are based on a Bit Error Ratio of 1e^–12.
5. Using 80 MHz sinusoidal jitter only in the absence of deterministic and random jitter.
6. Stimulus signal includes 0.4UI of DJ and 0.17UI of RJ. RX equalizer is enabled.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
18