XC5VLX110T-2FFG1738I Datasheet, PDF (78/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 95: Global Clock Setup and Hold With PLL in Source-Synchronous Mode (Cont’d)
Symbol
Description
T_PSPLL0/ T_PHPLL0 No Delay Global Clock and IFF⁽²⁾ with PLL in
Source-Synchronous Mode
Device
XC5VTX150T
Speed Grade
-3
-2
-1
N/A
–0.31 –0.29
1.41
1.47
XC5VTX240T
N/A
–0.31 –0.29
1.61
1.66
XC5VFX30T
–0.10
1.40
–0.09
1.46
–0.08
1.55
XC5VFX70T
–0.12
1.38
–0.10
1.44
–0.09
1.53
XC5VFX100T
–0.18
1.51
–0.18
1.60
–0.18
1.71
XC5VFX130T
–0.12
1.66
–0.11
1.76
–0.09
1.92
XC5VFX200T
N/A
–0.12 –0.10
1.94
2.06
Units
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage. These measurements include PLL CLKOUT0 jitter.
2. IFF = Input Flip-Flop or Latch.
3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
78