XC5VLX110T-2FFG1738I Datasheet, PDF (70/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 91: Global Clock Setup and Hold Without DCM or PLL (Cont’d)
Symbol
T_PSFD/ T_PHFD
Description
Full Delay (Legacy Delay or Default Delay)
Global Clock and IFF⁽²⁾ without DCM or PLL
Device
XC5VTX150T
XC5VTX240T
XC5VFX30T
XC5VFX70T
XC5VFX100T
XC5VFX130T
XC5VFX200T
Speed Grade
-3
-2
-1
N/A
2.35
2.59
–0.82 –0.82
N/A
2.59
2.87
–0.85 –0.85
2.05
–0.27
2.25
–0.27
2.57
–0.27
1.85
–0.30
2.06
–0.30
2.35
–0.30
2.20
–0.42
2.38
–0.42
2.66
–0.42
2.33
–0.55
2.59
–0.54
2.95
–0.54
N/A
2.52
2.81
–0.43 –0.43
Units
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Setup and Hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the
Global Clock input signal using the slowest process, highest temperature, and lowest voltage. Hold time is measured relative to the Global
Clock input signal using the fastest process, lowest temperature, and highest voltage.
2. IFF = Input Flip-Flop or Latch
3. A Zero "0" Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed "best-case", but if a "0"
is listed, there is no positive hold time.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
70