XC5VLX110T-2FFG1738I Datasheet, PDF (42/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Input Serializer/Deserializer Switching Characteristics
Table 62: ISERDES Switching Characteristics
Symbol
Description
Setup/Hold for Control Lines
T_{ISCCK_BITSLIP}/ T_{ISCKC_BITSLIP}
BITSLIP pin Setup/Hold with respect to CLKDIV
T_{ISCCK_CE} / T_{ISCKC_CE(2)}
CE pin Setup/Hold with respect to CLK (for CE1)
T_{ISCCK_CE2} / T_{ISCKC_CE2(2)}
CE pin Setup/Hold with respect to CLKDIV (for CE2)
Setup/Hold for Data Lines
T_{ISDCK_D} /T_{ISCKD_D}
D pin Setup/Hold with respect to CLK
T_{ISDCK_DDLY} /T_{ISCKD_DDLY}
T_{ISDCK_DDR} /T_{ISCKD_DDR}
DDLY pin Setup/Hold with respect to CLK (using
IODELAY)
D pin Setup/Hold with respect to CLK at DDR mode
T_{ISDCK_DDLY_DDR}
T_{ISCKD_DDLY_DDR}
Sequential Delays
D pin Setup/Hold with respect to CLK at DDR mode
(using IODELAY)
T_{ISCKO_Q}
Propagation Delays
CLKDIV to out at Q pin
T_{ISDO_DO}
D input to DO output pin
Notes:
1. Recorded at 0 tap value.
2. T_{ISCCK_CE2} and T_{ISCKC_CE2} are reported as T_{ISCCK_CE}/T_{ISCKC_CE} in TRACE report.
Speed Grade
-3
-2
-1
Units
0.10
0.11
0.12
ns
0.00
0.00
0.00
0.43
0.49
0.59
ns
–0.24 –0.24 –0.24
0.03
0.04
0.06
ns
0.11
0.13
0.15
0.34
0.37
0.39
ns
–0.12 –0.12 –0.12
0.31
0.33
0.36
ns
–0.09 –0.09 –0.08
0.34
0.37
0.39
ns
–0.12 –0.12 –0.12
0.31
0.33
0.36
ns
–0.09 –0.09 –0.08
0.46
0.51
0.60
ns
0.20
0.22
0.26
ns
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
42