XC5VLX110T-2FFG1738I Datasheet, PDF (29/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Table 52: Register-to-Register Performance (Cont’d)
Description
Dedicated Arithmetic Logic
DSP48E Quad 12-bit Adder/Subtracter
DSP48E Dual 24-bit Adder/Subtracter
DSP48E 48-bit Adder/Subtracter
DSP48E 48-bit Counter
DSP48E 48-bit Comparator
DSP48E 25 x 18 bit Pipelined Multiplier
DSP48E Direct 4-tap FIR Filter Pipelined
DSP48E Systolic n-tap FIR Filter Pipelined
Notes:
1. Device used is the XC5VLX50T- FF1136
Register-to-Register (with I/O Delays)
Speed Grade
-3
-2
-1
550
500
450
550
500
450
550
500
450
550
500
450
550
500
450
550
500
450
510
458
397
550
500
450
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Table 53: Interface Performances
Description
Networking Applications
SFI-4.1 (SDR LVDS Interface)⁽¹⁾
SPI-4.2 (DDR LVDS Interface)⁽²⁾
Memory Interfaces
DDR⁽³⁾
DDR2⁽⁴⁾
QDR II SRAM⁽⁵⁾
RLDRAM II⁽⁶⁾
-3
710 MHz
1.25 Gb/s
200 MHz
333 MHz
300 MHz
333 MHz
Speed Grade
-2
710 MHz
1.25 Gb/s
200 MHz
300 MHz
300 MHz
300 MHz
-1
645 MHz
1.0 Gb/s
200 MHz
267 MHz
250 MHz
250 MHz
Notes:
1. Performance defined using design implementation described in application note XAPP856: SFI-4.1 16-Channel SDR Interface with Bus
Alignment
2. Performance defined using design implementation described in application note XAPP860: 16-Channel, DDR LVDS Interface with Real-time
Window Monitoring
3. Performance defined using design implementation described in application note XAPP851: DDR SDRAM Controller
4. Performance defined using design implementation described in application note XAPP858: High-Performance DDR2 SDRAM Interface Data
Capture
5. Performance defined using design implementation described in application note XAPP853: QDRII SRAM Interface
6. Performance defined using design implementation described in application note XAPP852: Synthesizable RLDRAM II Controller
DS202 (v5.3) May 5, 2010
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Product Specification
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