XC5VLX110T-2FFG1738I Datasheet, PDF (53/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Clock Buffers and Networks
Table 71: Global Clock Switching Characteristics (Including BUFGCTRL)
Symbol
Description
Devices
T_{BCCCK_CE}/T_{BCCKC_CE(1)}
CE pins Setup/Hold
All
T_{BCCCK_S}/T_{BCCKC_S(1)}
S pins Setup/Hold
All
T_{BCCKO_O(2)}
Maximum Frequency
F_MAX
BUFGCTRL delay from
I0/I1 to O
LX20T
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX70T,
FX100T, and FX130T
FX30T
LX155 and LX155T
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
Global clock tree (BUFG)
LX20T
LX30, LX30T, LX50, LX50T,
LX85, LX85T, LX110, LX110T,
SX35T, SX50T, FX30T, and
FX70T
LX155, LX155T, and FX100T
FX130T
LX220, LX220T, LX330,
LX330T, SX95T, SX240T,
TX150T, TX240T, and FX200T
Speed Grade
-3
-2
-1
0.27
0.27
0.31
0.00
0.00
0.00
0.27
0.27
0.31
0.00
0.00
0.00
N/A
0.24
0.30
0.19
0.22
0.25
0.23
0.23
0.25
0.12
0.14
0.30
N/A
0.22
0.25
N/A
667
600
710
667
600
650
600
550
550
500
450
N/A
500
450
Units
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
Notes:
1. T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These
parameters do not apply to the BUFGMUX_VIRTEX4 primitive that assures glitch-free operation. The other global clock setup and hold times
are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between
clocks.
2. T_{BGCKO_O} (BUFG delay from I0 to O) values are the same as T_{BCCKO_O} values.
Table 72: Input/Output Clock Switching Characteristics (BUFIO)
Symbol
Description
T_{BUFIOCKO_O}
Maximum Frequency
F_MAX
Clock to out delay from I to O
I/O clock tree (BUFIO)
Speed Grade
-3
-2
-1
1.08
1.16
1.29
Units
ns
710
710
644
MHz
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
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