XC5VLX110T-2FFG1738I Datasheet, PDF (83/91 Pages) Xilinx, Inc – Virtex-5 FPGA Packaging and Pinout Specification

Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-5 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 98: Duty Cycle Distortion and Clock-Tree Skew
Symbol
T_{DCD_CLK}
T_CKSKEW
Description
Global Clock Tree Duty Cycle Distortion⁽¹⁾
Global Clock Tree Skew⁽²⁾
Device
All
XC5VLX20T
XC5VLX30
Speed Grade
-3
-2
-1
0.12
0.12
0.12
N/A
0.24
0.25
0.21
0.22
0.22
Units
ns
ns
ns
XC5VLX30T
0.21
0.22
0.22
ns
XC5VLX50
0.26
0.27
0.28
ns
XC5VLX50T
0.26
0.27
0.28
ns
XC5VLX85
0.42
0.43
0.45
ns
XC5VLX85T
0.42
0.43
0.45
ns
XC5VLX110
0.48
0.50
0.51
ns
XC5VLX110T
0.48
0.50
0.51
ns
XC5VLX155
0.82
0.85
0.88
ns
XC5VLX155T
0.82
0.85
0.88
ns
XC5VLX220
N/A
1.07
1.10
ns
XC5VLX220T
N/A
1.07
1.10
ns
XC5VLX330
N/A
1.25
1.29
ns
XC5VLX330T
N/A
1.25
1.29
ns
XC5VSX35T
0.38
0.39
0.39
ns
XC5VSX50T
0.43
0.44
0.45
ns
XC5VSX95T
N/A
0.72
0.74
ns
XC5VSX240T
N/A
1.32
1.36
ns
XC5VTX150T
N/A
0.70
0.73
ns
XC5VTX240T
N/A
0.97
1.00
ns
XC5VFX30T
0.34
0.35
0.35
ns
XC5VFX70T
0.41
0.42
0.43
ns
XC5VFX100T
0.82
0.84
0.86
ns
XC5VFX130T
0.82
0.84
0.86
ns
XC5VFX200T
N/A
1.24
1.29
ns
T_{DCD_BUFIO}
T_BUFIOSKEW
T_{DCD_BUFR}
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock region
Regional clock tree duty cycle distortion
All
0.10
0.10
0.10
ns
All
0.07
0.07
0.08
ns
All
0.25
0.25
0.25
ns
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases
where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical
rise/fall times.
2. The T_CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to the application.
DS202 (v5.3) May 5, 2010
www.xilinx.com
Product Specification
83