DS581 Datasheet, PDF (9/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 1: XPS EPC IP Core Design Parameters (Contd)
Generic Feature/Description
Parameter Name
Allowable Values
Default
Value
G32
Cycle time of write
signal (PRH_Wr_n)
C_PRHx_WR_
CYCLE^(4,16,17)
Integer number of
picoseconds
User must
set
values.⁽¹⁴⁾
Refer
targeted
device’s
data
sheet.
Data bus (PRH_Data)
G33
setup with respect to
falling edge of write
C_PRHx_DATA_
TSU^(4,15)
signal (PRH_Wr_n)
Integer number of
picoseconds
User must
set
values.⁽¹⁴⁾
Refer
targeted
device’s
data
sheet.
Data bus (PRH_Data)
G34
hold with respect to
rising edge of write
C_PRHx_DATA_
TH^(4,17)
signal (PRH_Wr_n)
Integer number of
picoseconds
User must
set
values.⁽¹⁴⁾
Refer
targeted
device’s
data
sheet.
G35
Minimum pulse width of C_PRHx_RDN_
read signal (PRH_Rd_n) WIDTH^(4,18,19,20)
Integer number of
picoseconds
User must
set
values.⁽¹⁴⁾
Refer
targeted
device’s
data
sheet.
G36
Cycle time of read signal C_PRHx_RD_
(PRH_Rd_n)
CYCLE^(4,19,20)
Integer number of
picoseconds
User must
set
values.⁽¹⁴⁾
Refer
targeted
device’s
data
sheet.
Data bus (PRH_Data)
G37
validity from falling edge C_PRHx_DATA_
of read signal
TOUT^(4,18)
(PRH_Rd_n)
Integer number of
picoseconds
User must
set
values.⁽¹⁴⁾
Refer
targeted
device’s
data
sheet.
VHDL
Type
integer
integer
integer
integer
integer
integer
DS581 September 16, 2009
www.xilinx.com
9
Product Specification