DS581 Datasheet, PDF (16/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 3: XPS EPC IP Core Parameter - Port Dependencies (Contd)
Generic
or Port
Name
Affects Depends
Description
If the device is configured for asynchronous mode:
• With peripheral clock support, the peripheral
clock input (PRH_Clk) must be driven high
externally
• PRH_RNW is driven high as PRH_Rd_n and
P43,
G24 C_PRHx_SYNC
P49, P50,
-
PRH_Wr_n should be used as read and write
strobe
P51, P52
• With data width matching enabled, the XPS
EPC drives PRH_Burst to its default low
If the device is configured for synchronous mode:
• The XPS EPC drives PRH_Rd_n and
PRH_Wr_n outputs to their default state of
high since PRH_RNW output is used as
read/write strobe
C_PRHx_BUS_
G25 _MULTIPLEX
P47
PRH_ADS is driven low if the device does not use
-
multiplexed address and data bus i.e.
C_PRHx_BUS_MULTIPLEX = 0
I/O Signals
P5 PLB_masterID
-
G5
The PLB master ID is determined by the
C_SPLB_MID_WIDTH parameter
P7 PLB_BE
-
G3
The number of byte enables for the PLB data bus
is determined by the C_SPLB_DWIDTH parameter
P10 PLB_wrDBus
-
G3
The PLB data bus width is determined by the
C_SPLB_DWIDTH parameter
P33 Sl_rdDBus
-
G3
The width of the PLB slave read data bus is
determined by the C_SPLB_DWIDTH parameter
P36 Sl_MBusy
-
G6
The width of PLB slave busy is determined by the
C_SPLB_NUM_MASTERS parameter
P37 Sl_MWrErr
-
G6
The width of PLB slave write error is determined by
the C_SPLB_NUM_MASTERS parameter
P38 Sl_MRdErr
-
G6
The width of PLB slave read error is determined by
the C_SPLB_NUM_MASTERS parameter
P42 Sl_MIRQ
The width of PLB slave master interrupt request is
-
G6
determined by the C_SPLB_NUM_MASTERS
parameter
P43 PRH_Clk
PRH_Clk is selected as operating clock only if the
device is configured for synchronous mode with
peripheral clock support i.e. C_PRHx_SYNC = 1
and C_PRH_CLK_SUPPORT = 1.
-
G15, G24 Asynchronous interface always operates on
SPLB_Clk. Therefore, if no device is configured for
synchronous mode with peripheral clock support
enabled then the input PRH_Clk must be driven
high
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DS581 September 16, 2009
Product Specification