DS581 Datasheet, PDF (13/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Table 2: XPS EPC IP Core I/O Signal Description (Contd)
Port
Signal Name
Interface
Signal
Type
Initial
State
Description
P24 PLB_rdPendPri[0 : 1]
PLB
I
-
PLB pending read request
priority
P25 PLB_reqPri[0 : 1]
PLB
I
-
PLB current request priority
P26 PLB_TAttribute[0 : 15]
PLB
I
-
PLB transfer attribute
PLB Slave Interface Output Signals
P27 Sl_addrAck
PLB
O
0
Slave address acknowledge
P28 Sl_SSize[0 : 1]
PLB
O
0
Slave data bus size
P29 Sl_wait
PLB
O
0
Slave wait
P30 Sl_rearbitrate
PLB
O
0
Slave bus rearbitrate
P31 Sl_wrDAck
PLB
O
0
Slave write data acknowledge
P32 Sl_wrComp
PLB
O
0
Slave write transfer complete
P33
Sl_rdDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
O
0
Slave read data bus
P34 Sl_rdDAck
PLB
O
0
Slave read data acknowledge
P35 Sl_rdComp
PLB
O
0
Slave read transfer complete
P36
Sl_MBusy[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave busy
P37
Sl_MWrErr[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave write error
P38
Sl_MRdErr[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Slave read error
P39 Sl_wrBTerm
P40 Sl_rdWdAddr[0 : 3]
P41 Sl_rdBTerm
Unused PLB Slave Interface Output Signals
PLB
O
0
Slave terminate write burst
transfer
PLB
O
0
Slave read word address
PLB
O
0
Slave terminate read burst
transfer
P42
Sl_MIRQ[0 :
C_SPLB_NUM_MASTERS - 1]
PLB
O
0
Master interrupt request
P43 PRH_Clk⁽¹⁾
P44 PRH_Rst
P45
PRH_CS_n[0 : C_NUM_
PERIPHERALS - 1]
XPS EPC Signals
EPC
I
-
External peripheral clock input
EPC
I
-
External peripheral reset input
EPC
O
1
External peripheral chip select.
Active low signal
DS581 September 16, 2009
www.xilinx.com
13
Product Specification