DS581 Datasheet, PDF (31/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Figure Top x-ref 11
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32
SPLB_Ckl
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
04050607
PRH_CS_n
Address Phase
Data Phase
PRH_Addr
00
01
02
03
PRH_ADS
PRH_BE
01
PRH_Burst
PRH_Rdy
PRH_RNW
Device is always ready and transaction is to the memory
PRH_Daat
000
040
001 050
002 060
003 070
DS581_11_08
Figure 11: Synchronous Write Transactions to Device Memory When Bus is Multiplexed and Data Width
Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
Figure Top x-ref 12
Cycles
0 1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 28 29 30 31 32 33
SPLB_Ckl
SPLB_Rst
PLB_type[0:2]
0
PLB_size[0:3]
0
PLB_ABus[0:31]
20000000
PLB_PAValid
PLB_RNW
PLB_BE[0:3]
F
PLB_wrDBus[0:31]
00000000
Sl_RdDbus[0:31]
PRH_CS_n
Address Phase
Data Phase
04050607
PRH_Addr
00
01
02
03
PRH_ADS
PRH_BE
01
PRH_Burst
PRH_Rdy
PRH_RNW
Device is always ready for communication
PRH_Daat
000
040
001 050 002
060
003 070
DS581_12_080309
Figure 12: Synchronous Read Transactions to Device Memory When Bus is Multiplexed and Data Width
Matching is Enabled (C_PRH_CLK_SUPPORT = 0)
DS581 September 16, 2009
www.xilinx.com
31
Product Specification