DS581 Datasheet, PDF (18/50 Pages) Xilinx, Inc – PLB interface with byte enable support

XPS External Peripheral Controller (EPC) v1.02a
Allowable Parameter Combinations
When the peripheral devices are configured in non multiplexed mode, the C_PRH_MAX_AWIDTH
should be the maximum of C_PRHx_AWIDTH of all peripherals in the system i.e if C_NUM_
PERIPHERALS is 2, then C_PRH_MAX_AWIDTH should be maximum of C_PRH0_AWIDTH and
C_PRH1_AWIDTH.
C_PRH_MAX_DWIDTH should be the maximum of C_PRHx_DWIDTH of all peripherals in the
system i.e. if C_NUM_PERIPHERALS is 2, then C_PRH_MAX_DWIDTH should be maximum of
C_PRH0_DWIDTH and C_PRH1_DWIDTH.
If any of the peripheral devices are configured for a multiplexed address and data buses, then the
parameter C_PRH_MAX_ADWIDTH should be set as the maximum of the data bus and address bus of
the device(s) employing a multiplexed address and data bus. If all devices employ non-multiplexed
address and data buses, then C_PRH_MAX_ADWIDTH reflects the maximum of data bus width of all
external devices. Therefore, for any configuration the parameter C_PRH_MAX_ADWIDTH should be
greater than or equal to C_PRH_MAX_DWIDTH.
The generic C_PRH_CLK_SUPPORT is relevant only when the devices are configured for the
synchronous access i.e. C_PRHx_SYNC = 1. If more than one of the devices are synchronous, then
the frequency for the peripheral clock should be chosen as the minimum of the operating frequencies of
those devices.
The range specified by C_PRHx_BASEADDR and C_PRHx_HIGHADDR parameters must comprise a
contiguous range and the size of the range must be a power of two i.e. size of range = 2^m.
Furthermore, the ’m’ least significant bits of C_PRHx_BASEADDR must be zero. The base and high
address range assigned to different peripherals must be mutually exclusive. No default value will be
specified for C_PRHx_BASEADDR and C_PRHx_HIGHADDR in order to enforce that the user
configures these parameters with the actual values. If the values are not set for C_PRHx_BASEADDR
and C_PRHx_HIGHADDR a compiler error will be generated.
In order to access FIFO like structures within the external peripheral devices, C_PRHx_FIFO_ACCESS
must be set to ’1’. When FIFO access is enabled, C_PRHx_FIFO_OFFSET specifies the offset of the FIFO
in terms of number of byte locations from the base address (C_PRHx_BASEADDR) of the peripheral
and should be set to an offset that lies within the address range assigned to the peripheral device i.e.
C_PRHx_BASEADDR + C_PRHx_FIFO_OFFSET ≤ C_PRHx_HIGHADDR. Furthermore, the FIFO
offset should be within the range addressable by the address bus i.e. C_PRHx_FIFO_OFFSET < 2ⁿ
where n = C_PRHx_AWIDTH.
The width of the read/write strobe must be less than the cycle time of the corresponding access i.e.
C_PRHx_WRN_WIDTH < C_PRHx_WR_CYCLE and C_PRHx_RDN_WIDTH <
C_PRHx_RD_CYCLE. The value of device ready validity period must be less than the read/write
strobe width and the maximum pulse width of the device ready signal i.e. C_PRHx_RDY_TOUT <
minimum of C_PRHx_WRN_WIDTH, C_PRHx_RDN_WIDTH and C_PRHx_RDY_WIDTH. The time
period between two consecutive writes (when the data width matching is enabled) will be decided by
maximum of (C_PRHx_WR_CYCLE-C_PRHx_WRN_WIDTH), C_PRHx_CSN_TH and
C_PRHx_DATA_TH parameters. Similar calculation is applicable for consecutive reads.
Please make sure that you have configured the timing parameters properly while using XPS EPC IP
Core at different frequencies on various FPGA devices.
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DS581 September 16, 2009
Product Specification